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1. 发明授权

US06249449B1 Hierarchical encoder including timing and data detection devices for a content addressable memory 失效
标题翻译：分层编码器，包括用于内容可寻址存储器的定时和数据检测装置
公开(公告)号：US06249449B1
公开(公告)日：2001-06-19
申请号：US09428278
申请日：1999-10-27
申请人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
发明人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
IPC分类号： G11C1504
CPC分类号： G06F17/30982 , G06F7/74 , G11C15/04
摘要： An associative memory to which an encoder is applied has a plurality of associative memory subblocks each having a plurality of memory words. A hit flag resulting from match retrieval of retrieval data and the contents of the memory word, and an empty flag indicating whether or not the contents of the memory word are valid as objects for match retrieval are output from each memory word of each associative memory subblock. The address of an invalid memory word is readily controllable since the address of the memory word corresponding to the empty flag can be output as in a case where the address of the memory word corresponding to the hit flag is output. Moreover, since the hit flag and the empty flag are allowed to share a detection line with each other for common use in this encoder, the layout area of the associative memory is reduced and it is possible to build up a high-density associative memory.
摘要翻译：应用编码器的关联存储器具有多个相关存储器子块，每个具有多个存储器字。从检索数据的匹配检索和存储器字的内容产生的命中标记，以及指示存储器字的内容是否作为用于匹配检索的对象是否有效的空标志从每个相关存储器子块的每个存储器字输出。无效存储器字的地址容易被控制，因为与输出与命中标志相对应的存储器字的地址的情况下可以输出与空标志相对应的存储字的地址。此外，由于允许命中标志和空标志在该编码器中共同使用检测线，所以关联存储器的布局区域减少，并且可以建立高密度关联存储器。

2. 发明授权

US5999434A Hierarchical encoder including timing and data detection devices for a content addressable memory 失效
标题翻译：分层编码器，包括用于内容可寻址存储器的定时和数据检测装置
公开(公告)号：US5999434A
公开(公告)日：1999-12-07
申请号：US910028
申请日：1997-08-12
申请人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
发明人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
IPC分类号： G06F7/74 , G06F17/30 , G11C15/04
CPC分类号： G06F17/30982 , G06F7/74 , G11C15/04
摘要： An associative memory to which an encoder is applied has a plurality of associative memory subblocks each having a plurality of memory words. A hit flag resulting from match retrieval of retrieval data and the contents of the memory word, and an empty flag indicating whether or not the contents of the memory word are valid as objects for match retrieval are output from each memory word of each associative memory subblock. The address of an invalid memory word is readily controllable since the address of the memory word corresponding to the empty flag can be output as in a case where the address of the memory word corresponding to the hit flag is output. Moreover, since the hit flag and the empty flag are allowed to share a detection line with each other for common use in this encoder, the layout area of the associative memory is reduced and it is possible to build up a high-density associative memory.
摘要翻译：应用编码器的关联存储器具有多个相关存储器子块，每个具有多个存储器字。从检索数据的匹配检索和存储器字的内容产生的命中标记，以及指示存储器字的内容是否作为用于匹配检索的对象是否有效的空标志从每个相关存储器子块的每个存储器字输出。无效存储器字的地址容易被控制，因为与输出与命中标志相对应的存储器字的地址的情况下可以输出与空标志相对应的存储字的地址。此外，由于允许命中标志和空标志在该编码器中共同使用检测线，所以关联存储器的布局区域减少，并且可以建立高密度关联存储器。

3. 发明授权

US5619446A Hierarchical encoder including timing and data detection devices for a content addressable memory 失效
标题翻译：分层编码器，包括用于内容可寻址存储器的定时和数据检测装置
公开(公告)号：US5619446A
公开(公告)日：1997-04-08
申请号：US1751
申请日：1993-01-07
申请人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
发明人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
IPC分类号： G06F7/74 , G06F17/30 , G11C15/04 , G06F12/02
CPC分类号： G06F7/74 , G06F17/30982 , G11C15/04
摘要： A Content Addressable Memory (CAM) encoder comprises either a prefetch circuit or a flag data sense circuit. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and enables a large capacity CAM to operate at high speeds. Moreover, a semiconductor integrated circuit detects the differential current between the current flowing through a first signal line and the reference current flowing through a second signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock and operates as the timing control circuit to predict the termination of the encoding operation. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed.
摘要翻译：内容可寻址存储器（CAM）编码器包括预取电路或标志数据检测电路。当第一优先子块中的命中信号被编码时，第二优先级子块中的命中信号可被存储在预取电路中。因此，在没有子块到子块切换时间的情况下执行编码操作，并且能够使大容量CAM以高速运行。此外，半导体集成电路检测流过第一信号线的电流与流过第二信号线的参考电流之间的差分电流。此外，它可以作为数字检测电路来操作以检测子块中的命中信号的数量，并且用作定时控制电路以预测编码操作的终止。因此，该半导体集成电路可以允许编码器以高速非常有效地进行编码。

4. 发明授权

US5726942A Hierarchical encoder including timing and data detection devices for a content addressable memory 失效
标题翻译：分层编码器，包括用于内容可寻址存储器的定时和数据检测装置
公开(公告)号：US5726942A
公开(公告)日：1998-03-10
申请号：US760292
申请日：1996-12-04
申请人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
发明人： Masato Yoneda , Hiroshi Sasama , Naoki Kanazawa
IPC分类号： G06F7/74 , G06F17/30 , G11C15/04 , G11C7/06
CPC分类号： G06F7/74 , G06F17/30982 , G11C15/04
摘要： A encoder has a prefetch circuit or a flag data sense circuit built into the priority encoder provided for a CAM block. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and this makes the encoder best suitable for a large capacity CAM which is required to operate at high speed. Moreover, a semiconductor integrated circuit of the present invention detects the differential current between the current flowing through one signal line and the reference current flowing through the other signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock, and it can operate as the timing control circuit to previously notify the encode termination of the hit signal in the subblock of the encoder described above. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed. Moreover, a dynamic sense amplifier is able to operate with a great operating margin.
摘要翻译：编码器具有内置在为CAM块提供的优先编码器中的预取电路或标志数据检测电路。当第一优先子块中的命中信号被编码时，第二优先级子块中的命中信号可被存储在预取电路中。因此，在没有子块到子块切换时间的情况下执行编码操作，这使得编码器最适合于高速操作所需的大容量CAM。此外，本发明的半导体集成电路检测流过一条信号线的电流与流过另一条信号线的基准电流之间的差分电流。此外，它可以作为号码检测电路来操作以检测子块中的命中信号的数量，并且它可以作为定时控制电路进行操作以预先通知上述编码器的子块中的命中信号的编码终止。因此，该半导体集成电路可以允许编码器以高速非常有效地进行编码。此外，动态感测放大器能够以较大的运行裕度运行。

5. 发明授权

US5592407A Associative memory 失效
标题翻译：关联记忆
公开(公告)号：US5592407A
公开(公告)日：1997-01-07
申请号：US393072
申请日：1995-02-23
申请人： Masahiro Konishi , Hiroshi Sasama , Masato Yoneda
发明人： Masahiro Konishi , Hiroshi Sasama , Masato Yoneda
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： In an associative memory comprising a function to extend data width, for which match retrieval is to be conducted, up to a plurality of words, that is, a function to detect total match data when match is respectively detected for a plurality of continuous retrievals, power consumption can be reduced by making active only the necessary areas under the condition that the whole circuit is no longer required to be made active through execution of the current retrieval only to the blocks for which match is detected in the preceding retrieval during a plurality of continuous retrieving operations and/or its adjacent blocks.
摘要翻译：在一个关联存储器中，包括扩展数据宽度的功能，为了进行匹配检索，多达一个单词，即分别检测多个连续检索的匹配时检测总匹配数据的功能，在通过执行当前检索的整个电路不再需要被激活的条件下，在多个连续检索操作和/或其相邻块。

6. 发明授权

US5555397A Priority encoder applicable to large capacity content addressable memory 失效
标题翻译：优先编码器适用于大容量内容可寻址存储器
公开(公告)号：US5555397A
公开(公告)日：1996-09-10
申请号：US2463
申请日：1993-01-07
申请人： Hiroshi Sasama , Masato Yoneda
发明人： Hiroshi Sasama , Masato Yoneda
IPC分类号： G06F7/74 , G11C15/04 , G06F7/00
CPC分类号： G06F7/74 , G11C15/04
摘要： A priority encoder is provided with priority circuitry for sequentially producing priority-ordered output signals and encoding circuitry for encoding the output signal. Small input, small unit priority circuits are used to form the priority circuitry into a hierarchical structure. An OR output of a small unit priority circuit in a lower hierarchy is used as an input signal of another small unit priority circuit in a higher hierarchy. An output signal of the priority circuit in the higher hierarchy has an address which corresponds to the address of the one input signal and is made an enable signal of the priority circuit in the lower hierarchy. The priority encoder, though simple in structure and formed with a small number of elements, operates at a high speed. Moreover, an encoder with a prefetch circuit is built into the priority encoder provided for a CAM block. While a "hit" signal in a first priority subblock is being encoded, a hit signal in a second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time, making the encoder best suitable for a large capacity, high speed CAM.
摘要翻译：优先编码器具有用于顺序产生优先排序的输出信号的优先电路和用于编码输出信号的编码电路。小输入，小单元优先级电路用于将优先级电路组成层次结构。较低层次的小单元优先电路的OR输出被用作较高级别的另一小单元优先电路的输入信号。较高级别的优先级电路的输出信号具有对应于一个输入信号的地址的地址，并被制成低层次的优先级电路的使能信号。优先编码器虽然结构简单，形成少量元件，但运行速度很快。此外，具有预取电路的编码器内置在为CAM块提供的优先编码器中。当第一优先子块中的“命中”信号被编码时，第二优先级子块中的命中信号可被存储在预取电路中。因此，在没有子块到子块切换时间的情况下执行编码操作，使得编码器最适合于大容量，高速CAM。

7. 发明授权

US5978245A Associative memory device having circuitry for storing a coincidence line output 失效
标题翻译：具有用于存储重合线输出的电路的关联存储器件
公开(公告)号：US5978245A
公开(公告)日：1999-11-02
申请号：US947877
申请日：1997-10-09
申请人： Ryuichi Hata , Hiroshi Sasama , Masato Yoneda
发明人： Ryuichi Hata , Hiroshi Sasama , Masato Yoneda
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： An associative memory device in which a coincident output is held by each word and aging for word data can be efficiently performed such that the word data is made valid or invalid on the basis of the information. The associative memory device includes a plurality of words for storing data, for detecting the coincidence/non-coincidence between the data stored in the plurality of respective words and input search data. Each word further includes a memory for storing a coincidence line output by a searching operation, a storage memory for storing data representing whether the corresponding word is subjected to a searching operation or is available to write new data therein, a circuit for simultaneously setting/resetting the contents of the storage memory, and circuit for resetting/setting the memory for storing the coincidence line output by the storage memory.
摘要翻译：可以有效地执行其中由每个字保持一致输出并且对于字数据进行老化的关联存储器装置，使得基于该信息使字数据有效或无效。关联存储装置包括用于存储数据的多个字，用于检测存储在多个相应字中的数据与输入的搜索数据之间的一致/不一致。每个字还包括用于存储通过搜索操作输出的符合线的存储器，用于存储表示相应字是否经过搜索操作或可用于在其中写入新数据的数据的存储器，用于同时设置/重置的电路存储存储器的内容，以及用于复位/设置用于存储由存储存储器输出的重合线的存储器的电路。

8. 发明授权

US5946704A Associative memory to retrieve a plurality of words 失效
标题翻译：用于检索多个单词的关联存储器
公开(公告)号：US5946704A
公开(公告)日：1999-08-31
申请号：US386868
申请日：1995-02-10
申请人： Masato Yoneda , Hiroshi Sasama
发明人： Masato Yoneda , Hiroshi Sasama
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： The associative memory may include a plurality of memory words storing storage data, flag registers each corresponding to an associated one of the plurality of memory words, a gate circuit having signal lines each corresponding to an associated one of the plurality of memory words and a priority encoder for designating one of the memory words. An address converter may convert the address of one of the memory words output from the priority encoder into a representative address. The storage data may include a pair of attribute indicative of positioning in the data group to which the storage data belongs. In at least one embodiment, match lines each corresponding to an associated one of the plurality of memory words and a plurality of encode coding circuits may be provided.
摘要翻译：关联存储器可以包括存储存储数据的多个存储字，各自对应于多个存储字中相关联的一个的标志寄存器，具有各自对应于多个存储器字中相关联的一个存储器字的信号线的门电路和优先级用于指定其中一个存储字的编码器。地址转换器可以将从优先编码器输出的一个存储字的地址转换为代表地址。存储数据可以包括指示存储数据所属的数据组中的定位的一对属性。在至少一个实施例中，可以提供与多个存储器字中的相关联的一个对应的匹配行和多个编码编码电路。

9. 发明授权

US5030525A Inorganic nonaqueous electrolytic solution type cell 失效
标题翻译：无机非水电解液型电池
公开(公告)号：US5030525A
公开(公告)日：1991-07-09
申请号：US565514
申请日：1990-08-10
申请人： Kaoru Hisatomi , Hiroshi Sasama , Kazuo Ishida , Shintaro Sekido
发明人： Kaoru Hisatomi , Hiroshi Sasama , Kazuo Ishida , Shintaro Sekido
IPC分类号： H01M2/12 , H01M2/16 , H01M6/14
CPC分类号： H01M6/14 , H01M2/1241 , H01M2/1666 , H01M2300/0017
摘要： An inorganic nonaqueous electrolytic solution type cell comprising a separator which is positioned between a negative electrode and a positive electrode, a bottom insulator which is positioned between a bottom of a cell container and a positive electrode, and an electrolytic solution comprising an electrolyte and an oxyhalide which is in the liquid state at room temperature and serves as an active material for a positive electrode and a solvent for the electrolytic solution, wherein each of the separator and the bottom insulator comprises a material selected from the group consisting of a microporous film of an ethylene-tetrafluoroethylene copolymer and a composite sheet of a microporous film of an ethylene-tetrafluoroethylene copolymer and a nonwoven glass fabric.

10. 发明授权

US5805493A Associative memory having a data registration device 失效
标题翻译：具有数据登记装置的关联存储器
公开(公告)号：US5805493A
公开(公告)日：1998-09-08
申请号：US571771
申请日：1995-12-13
申请人： Masahiro Konishi , Hiroshi Sasama
发明人： Masahiro Konishi , Hiroshi Sasama
IPC分类号： G06F17/30 , G11C15/00 , G11C15/04
CPC分类号： G06F17/30982 , G11C15/00 , G11C15/04
摘要： This invention provides an associative memory that includes a plurality of associative memory integrated circuits. Each of the associative memory integrated circuits includes a plurality of memory words and a data registration device. The data registration device stores a retrieval word into one of the plurality of memory words in response to control signal received from an external source if a first priority signal is not received from at least another one of the plurality of associative memory integrated circuits and if the one of the plurality of memory words is in an open state.
摘要翻译：本发明提供一种包括多个关联存储器集成电路的关联存储器。每个相关存储器集成电路包括多个存储字和数据注册装置。如果没有从多个关联存储器集成电路中的至少另一个存储器集成电路接收到第一优先级信号，则数据注册装置响应于从外部源接收的控制信号将检索词存储到多个存储器字中的一个存储器字中，多个存储器字中的一个处于打开状态。

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