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1. 发明申请

US20120187978A1 Methods and Circuits for Calibrating Multi-Modal Termination Schemes 有权
标题翻译：用于校准多模式终端方案的方法和电路
公开(公告)号：US20120187978A1
公开(公告)日：2012-07-26
申请号：US13349226
申请日：2012-01-12
申请人： Hajee Mohammed Shuaeb Fazeel , Amir Amirkhany , Gundlapalli Shanmukha Srinivas , Chaofeng Huang
发明人： Hajee Mohammed Shuaeb Fazeel , Amir Amirkhany , Gundlapalli Shanmukha Srinivas , Chaofeng Huang
IPC分类号： H03K19/003
CPC分类号： H03K19/017545 , G11C29/025 , G11C29/028 , H03K19/018514 , H03K19/018564
摘要： Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.
摘要翻译：公开了使用相对较少数量的外部校准焊盘来支持用于多个信令方案的不同的管芯端接（ODT）方案的方法和电路。这些方法和电路开发用于校准可能由相关联的通信电路使用的多个终止方案中的任何一个的控制信号。 ODT控制电路，完全或主要实例化的裸片，共享用于支持不同终端方案的电路资源，以节省芯片面积。

2. 发明授权

US08487650B2 Methods and circuits for calibrating multi-modal termination schemes 有权
标题翻译：用于校准多模式终端方案的方法和电路
公开(公告)号：US08487650B2
公开(公告)日：2013-07-16
申请号：US13349226
申请日：2012-01-12
申请人： Hajee Mohammed Shuaeb Fazeel , Amir Amirkhany , Gundlapalli Shanmukha Srinivas , Chaofeng Huang
发明人： Hajee Mohammed Shuaeb Fazeel , Amir Amirkhany , Gundlapalli Shanmukha Srinivas , Chaofeng Huang
IPC分类号： H03K17/16
CPC分类号： H03K19/017545 , G11C29/025 , G11C29/028 , H03K19/018514 , H03K19/018564
摘要： Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.
摘要翻译：公开了使用相对较少数量的外部校准焊盘来支持用于多个信令方案的不同的管芯端接（ODT）方案的方法和电路。这些方法和电路开发用于校准可能由相关联的通信电路使用的多个终止方案中的任何一个的控制信号。 ODT控制电路，完全或主要实例化的裸片，共享用于支持不同终端方案的电路资源，以节省芯片面积。

3. 发明申请

US20120147944A1 HIGH RESOLUTION OUTPUT DRIVER 有权
标题翻译：高分辨率输出驱动器
公开(公告)号：US20120147944A1
公开(公告)日：2012-06-14
申请号：US13391383
申请日：2010-09-14
申请人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloof , Kun-Yung Chang
发明人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloof , Kun-Yung Chang
IPC分类号： H04L27/01
CPC分类号： H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要翻译：具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。

4. 发明授权

US08531206B2 High resolution output driver 有权
标题翻译：高分辨率输出驱动
公开(公告)号：US08531206B2
公开(公告)日：2013-09-10
申请号：US13391383
申请日：2010-09-14
申请人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloff , Kun-Yung Chang
发明人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloff , Kun-Yung Chang
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要翻译：具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。

5. 发明授权

US09484891B2 Multi-modal communication interface 有权
标题翻译：多模态通信接口
公开(公告)号：US09484891B2
公开(公告)日：2016-11-01
申请号：US13880960
申请日：2012-01-24
申请人： Amir Amirkhany , Chaofeng Huang
发明人： Amir Amirkhany , Chaofeng Huang
IPC分类号： H03K3/01 , H01L27/02 , H03K19/003 , H03K19/0185
CPC分类号： H03K3/01 , H01L27/0251 , H03K19/00315 , H03K19/018521 , H03K19/018528
摘要： An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage.
摘要翻译：集成电路支持使用不同输入/输出（IO）电压的多种通信模式。 IC包括在低电压模式下以低IO电压工作的低压通信电路和在高电压模式下以高IO电压工作的高压通信电路。低压通信电路包括在低于高IO电压的破坏性电压下具有敏感性的关键路径中的低压晶体管。因此，低压通信电路设置有保护电路以保护低压晶体管免受高10电压的影响。

6. 发明申请

US20130278296A1 Multi-Modal Communication Interface 有权
标题翻译：多模态通信接口
公开(公告)号：US20130278296A1
公开(公告)日：2013-10-24
申请号：US13880960
申请日：2012-01-24
申请人： Amir Amirkhany , Chaofeng Huang
发明人： Amir Amirkhany , Chaofeng Huang
IPC分类号： H03K3/01
CPC分类号： H03K3/01 , H01L27/0251 , H03K19/00315 , H03K19/018521 , H03K19/018528
摘要： An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage.
摘要翻译：集成电路支持使用不同输入/输出（IO）电压的多种通信模式。 IC包括在低电压模式下以低IO电压工作的低压通信电路和在高电压模式下以高IO电压工作的高压通信电路。低压通信电路包括在低于高IO电压的破坏性电压下具有敏感性的关键路径中的低压晶体管。因此，低压通信电路设置有保护电路以保护低压晶体管免受高10电压的影响。

7. 发明授权

US09165615B2 Coded differential intersymbol interference reduction 有权
标题翻译：编码差分符号间干扰减少
公开(公告)号：US09165615B2
公开(公告)日：2015-10-20
申请号：US13636515
申请日：2011-03-14
申请人： Amir Amirkhany , Aliazam Abbasfar , Kambiz Kaviani , Wendemagegnehu Beyene , Carl Werner
发明人： Amir Amirkhany , Aliazam Abbasfar , Kambiz Kaviani , Wendemagegnehu Beyene , Carl Werner
IPC分类号： G11C8/00 , G11C7/10 , G11C7/02
CPC分类号： G11C7/1006 , G11C7/02
摘要： Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.
摘要翻译：编码器和解码器电路，用于对一系列代码字进行编码和解码一系列数据字。数据字包括L个符号。代码字包括M个符号，其中M大于L.一组紧密耦合的M个链路，用于在每一个码字序列中传送相应的符号。选择码字使得在一系列码字中的每两个连续码字之间，在M链路的子集上出现从低到高和高到低的相等数量的转换。

8. 发明申请

US20110184999A1 Linear Transformation Circuit 审中-公开
标题翻译：线性变换电路
公开(公告)号：US20110184999A1
公开(公告)日：2011-07-28
申请号：US13083473
申请日：2011-04-08
申请人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
发明人： Aliazam Abbasfar , Amir Amirkhany , Vladimir Stojanovic , Mark A. Horowitz
IPC分类号： G06F17/14
CPC分类号： G06J1/00
摘要： A first device includes a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit as an input to receive a vector having N digital values and an output to output N first output signals. The linear transformation circuit optionally includes a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H. The linear transformation circuit includes a digital-to-analog conversion (DAC) circuit coupled to the output of the sign-adjustment circuit. Outputs from the DAC circuit are summed to produce an output.
摘要翻译：第一装置包括用矩阵D进行乘法的线性变换电路。线性变换电路作为用于接收具有N个数字值的矢量和输出以输出N个第一输出信号的输入。线性变换电路可选地包括符号调整电路，用于根据一组系数H来调整包括至少M个N个第一输出信号的子集的符号。线性变换电路包括数模转换（DAC））电路耦合到符号调节电路的输出。来自DAC电路的输出相加以产生输出。

9. 发明授权

US09046909B2 On-chip regulator with variable load compensation 有权
标题翻译：具有可变负载补偿的片上调节器
公开(公告)号：US09046909B2
公开(公告)日：2015-06-02
申请号：US14241843
申请日：2012-08-31
申请人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
发明人： Brian S. Leibowitz , Michael D. Bucher , Lei Luo , Chaofeng Charlie Huang , Amir Amirkhany , Huy M. Nguyen , Hsuan-Jung (Bruce) Su , John Wilson
IPC分类号： G05F1/10 , G05F1/46 , G11C5/14
CPC分类号： G05F1/462 , G11C5/147
摘要： An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.
摘要翻译：集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。该电路根据数据从电压调节器抽取可变量的功率。电压调节器包括用于提供数据转变相关电流的第一电流产生电路。

10. 发明授权

US08917783B2 Resonance mitigation for high-speed signaling 有权
标题翻译：高速信令的共振减轻
公开(公告)号：US08917783B2
公开(公告)日：2014-12-23
申请号：US13129998
申请日：2009-12-03
申请人： Farshid Aryanfar , Aliazam Abbasfar , Amir Amirkhany
发明人： Farshid Aryanfar , Aliazam Abbasfar , Amir Amirkhany
IPC分类号： H04L27/00 , H04L25/02 , H04L25/03
CPC分类号： H04L25/0272 , H04L25/03878
摘要： The frequency response of a first component signal path of a differential signaling link is adjusted to off-set a notch in the frequency response from a corresponding notch in the frequency response of a second component signal path of the differential signaling link.
摘要翻译：差分信号链路的第一分量信号路径的频率响应被调整为在差分信令链路的第二分量信号路径的频率响应中的相应陷波的频率响应中偏移一个陷波。

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