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1. 发明申请

US20100057984A1 MEMORY HIERARCHY CONTAINING ONLY NON-VOLATILE CACHE 审中-公开
标题翻译：仅包含非易失性高速缓存的内存分层
公开(公告)号：US20100057984A1
公开(公告)日：2010-03-04
申请号：US12198513
申请日：2008-08-26
申请人： Yiran Chen , Hai Li , Hongyue Liu , Haiwen Xi , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Haiwen Xi , Song S. Xue
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0804 , G06F12/0868 , G06F12/0897 , G06F2212/2022 , G06F2212/2024 , G06F2212/222
摘要： A storage system that includes non-volatile main memory; non-volatile read cache; non-volatile write cache; and a data path operably coupled between the non-volatile write cache and the non-volatile read cache, wherein the storage system does not include any volatile cache and methods for retrieving and writing data throughout this memory hierarchy system.
摘要翻译：一种包含非易失性主存储器的存储系统; 非易失性读取缓存; 非易失性写缓存; 以及可操作地耦合在所述非易失性写入高速缓存和所述非易失性读取高速缓存之间的数据路径，其中所述存储系统不包括用于在所述存储器层级系统中检索和写入数据的任何易失性高速缓存和方法。

2. 发明授权

US08514605B2 MRAM diode array and access method 有权
标题翻译： MRAM二极管阵列和访问方式
公开(公告)号：US08514605B2
公开(公告)日：2013-08-20
申请号：US13611225
申请日：2012-09-12
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C5/08 , G11C27/00 , G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

3. 发明授权

US08296620B2 Data devices including multiple error correction codes and methods of utilizing 有权
标题翻译：数据设备包括多个纠错码和利用方法
公开(公告)号：US08296620B2
公开(公告)日：2012-10-23
申请号：US12198516
申请日：2008-08-26
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.
摘要翻译：一种使用至少一个数据块的方法，其中所述至少一个数据块包括用于存储数据的多个单元和至少一个误差标志位，所述方法包括：扫描所述数据块的错误; 确定数据块的错误率; 以及对所述至少一个数据块中的单元读取或写入的数据应用纠错码，其中，基于所述错误率应用所述纠错码，其中当所述错误率低于错误阈值，并且当错误率处于或高于错误阈值时应用强纠错码。

4. 发明申请

US20130003448A1 MRAM DIODE ARRAY AND ACCESS METHOD 有权
标题翻译： MRAM二极管阵列和访问方法
公开(公告)号：US20130003448A1
公开(公告)日：2013-01-03
申请号：US13611225
申请日：2012-09-12
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

5. 发明授权

US08289746B2 MRAM diode array and access method 有权
标题翻译： MRAM二极管阵列和访问方式
公开(公告)号：US08289746B2
公开(公告)日：2012-10-16
申请号：US12948824
申请日：2010-11-18
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C5/08 , G11C27/00 , G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

6. 发明申请

US20100037102A1 FAULT-TOLERANT NON-VOLATILE BUDDY MEMORY STRUCTURE 审中-公开
标题翻译：故障的非易失性存储结构
公开(公告)号：US20100037102A1
公开(公告)日：2010-02-11
申请号：US12269535
申请日：2008-11-12
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Alan Xuguang Wang , Song S. Xue
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Alan Xuguang Wang , Song S. Xue
IPC分类号： G06F11/16 , G06F11/00 , G06F12/08 , G06F12/00
CPC分类号： G11C29/846
摘要： Various embodiments of the present invention are generally directed to an apparatus and method for providing a fault-tolerant non-volatile buddy memory structure, such as a buddy cache structure for a controller in a data storage device. A semiconductor memory array of blocks of non-volatile resistive sense memory (RSM) cells is arranged to form a buddy memory structure comprising a first set of blocks in a first location of the array and a second set of blocks in a second location of the array configured to redundantly mirror the first set of blocks. A read circuit decodes a fault map which identifies a defect in a selected one of the first and second sets of blocks and concurrently outputs data stored in the remaining one of the first and second sets of blocks responsive to a data read operation upon said buddy memory structure.
摘要翻译：本发明的各种实施例通常涉及用于提供容错非易失性伙伴存储器结构的装置和方法，例如用于数据存储设备中的控制器的伙伴高速缓存结构。布置非易失性电阻式感测存储器（RSM）单元块的半导体存储器阵列以形成伙伴存储器结构，其包括阵列的第一位置中的第一组块和位于阵列的第二位置的第二组块阵列被配置为冗余地镜像第一组块。读取电路解码故障映射，其识别所述第一和第二组块中的所选择的一个中的缺陷，并响应于所述好友存储器上的数据读取操作，同时输出存储在第一组和第二组中的剩余块中的数据结构体。

7. 发明授权

US07936580B2 MRAM diode array and access method 有权
标题翻译： MRAM二极管阵列和访问方式
公开(公告)号：US07936580B2
公开(公告)日：2011-05-03
申请号：US12254414
申请日：2008-10-20
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C5/08 , G11C27/00 , G11C11/00 , G11C7/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。

8. 发明申请

US20100097852A1 MRAM DIODE ARRAY AND ACCESS METHOD 有权
标题翻译： MRAM二极管阵列和访问方法
公开(公告)号：US20100097852A1
公开(公告)日：2010-04-22
申请号：US12254414
申请日：2008-10-20
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C11/14 , G11C7/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。

9. 发明申请

US20100058125A1 DATA DEVICES INCLUDING MULTIPLE ERROR CORRECTION CODES AND METHODS OF UTILIZING 有权
标题翻译：包含多个错误修正码的数据设备和使用方法
公开(公告)号：US20100058125A1
公开(公告)日：2010-03-04
申请号：US12198516
申请日：2008-08-26
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.
摘要翻译：一种使用至少一个数据块的方法，其中所述至少一个数据块包括用于存储数据的多个单元和至少一个误差标志位，所述方法包括：扫描所述数据块的错误; 确定数据块的错误率; 以及对所述至少一个数据块中的单元读取或写入的数据应用纠错码，其中，基于所述错误率应用所述纠错码，其中当所述错误率低于错误阈值，并且当错误率处于或高于错误阈值时应用强纠错码。

10. 发明申请

US20110058409A1 MRAM DIODE ARRAY AND ACCESS METHOD 有权
标题翻译： MRAM二极管阵列和访问方法
公开(公告)号：US20110058409A1
公开(公告)日：2011-03-10
申请号：US12948824
申请日：2010-11-18
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C11/16 , G11C11/02
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

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