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1. 发明授权

US08030157B1 Liner protection in deep trench etching 失效
标题翻译：衬里保护深沟蚀刻
公开(公告)号：US08030157B1
公开(公告)日：2011-10-04
申请号：US12782050
申请日：2010-05-18
申请人： Habib Hichri , Ahmad D. Katnani , Kaushik A. Kumar , Narender Rana , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
发明人： Habib Hichri , Ahmad D. Katnani , Kaushik A. Kumar , Narender Rana , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
IPC分类号： H01L21/8242
CPC分类号： H01L21/76232
摘要： A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.
摘要翻译：在由衬底和形成在衬底上的第一层形成的半导体器件中形成沟槽的方法包括形成通过第一层到衬底的初始沟槽，初始沟槽的直径从第一直径减小到第二直径，第二直径在比第一直径更靠近基板的距离处被测量; 通过正交离子注入将沟槽暴露于掺杂剂以形成沟槽的掺杂区域侧壁; 并蚀刻沟槽以去除至少一些掺杂区域。

2. 发明申请

US20090117360A1 SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT 审中-公开
标题翻译：自组装材料模式转移对比增强
公开(公告)号：US20090117360A1
公开(公告)日：2009-05-07
申请号：US11933760
申请日：2007-11-01
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Habib Hichri , Louis L. Hsu , Kaushik A. Kumar , Carl Radens , Shahab Siddiqui , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Habib Hichri , Louis L. Hsu , Kaushik A. Kumar , Carl Radens , Shahab Siddiqui , Chih-Chao Yang
IPC分类号： G03C1/73 , B05D3/00 , B32B27/06
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y30/00 , H01L21/0338
摘要： A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region.
摘要翻译：含有至少两个不混溶的聚合物嵌段组分的非光敏聚合物抗蚀剂沉积在平面上。将非光敏聚合物抗蚀剂退火以允许不相容组分的相分离并显影以除去至少两种聚合物嵌段组分中的至少一种。在聚合物抗蚀剂中形成纳米尺度特征，即纳米尺度的特征，包括具有纳米级尺寸的至少一个凹陷区域。聚合物抗蚀剂的顶表面通过暴露于能量束而被改进以提高耐蚀刻性，这允许图案化聚合物抗蚀剂的顶表面变得更耐蚀刻工艺和化学物质。两种类型表面之间的增强的耐蚀刻比提供了改善的图像对比度和具有顶表面和至少一个凹陷区域的区域之间的保真度。

3. 发明授权

US08901006B2 ARC residue-free etching 有权
标题翻译：无ARC残留蚀刻
公开(公告)号：US08901006B2
公开(公告)日：2014-12-02
申请号：US13081020
申请日：2011-04-06
申请人： Xiang Hu , Richard S. Wise , Habib Hichri , Catherine Labelle
发明人： Xiang Hu , Richard S. Wise , Habib Hichri , Catherine Labelle
IPC分类号： H01L21/3213 , H01L21/311 , H01L27/11 , H01L21/3105
CPC分类号： H01L23/48 , H01L21/31055 , H01L21/311 , H01L21/31111 , H01L21/3213 , H01L21/32139 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.
摘要翻译：在图案转印和后续短路过程中的抗反射残余物通过使用下面的牺牲层来确保完全去除抗反射层而消除。实施例包括在导电层（例如硅衬底）上形成硬掩模层，在硬掩模层上形成牺牲层，在牺牲层上形成光学色散层，在光学色散上形成硅抗反射涂层在硅抗反射涂层上形成光致抗蚀剂层，其中光致抗蚀剂层限定图案，蚀刻以将图案转移到硬掩模层，以及剥离至少光学色散层和牺牲层。

4. 发明授权

US08492280B1 Method for simultaneously forming features of different depths in a semiconductor substrate 失效
标题翻译：同时形成半导体衬底中不同深度的特征的方法
公开(公告)号：US08492280B1
公开(公告)日：2013-07-23
申请号：US13465050
申请日：2012-05-07
申请人： Habib Hichri , Xi Li , Richard S. Wise
发明人： Habib Hichri , Xi Li , Richard S. Wise
IPC分类号： H01L21/311
CPC分类号： H01L21/3065 , H01L21/76229 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
摘要翻译：本发明的实施例可以包括首先提供包括半导体衬底，半导体衬底上的掩埋氧化物层，掩埋氧化物层上的绝缘体上半导体层，绝缘体上半导体上的氮化物层层和氮化物层上的氧化硅层。然后在氧化硅层，氮化物层，绝缘体上半导体层和掩埋氧化物层上形成具有比第一开口更小的横截面面积的第一开口和第二开口。然后用第一蚀刻气体蚀刻第一开口和第二开口。然后用第二蚀刻气体蚀刻第一开口和第二开口，第二蚀刻气体包括第一蚀刻气体和卤化硅化合物，例如四氟化硅或四氯化硅。在一个实施方案中，第一蚀刻气体包括溴化氢，三氟化氮和氧。

5. 发明授权

US08642475B2 Integrated circuit system with reduced polysilicon residue and method of manufacture thereof 有权
标题翻译：减少多晶硅残渣的集成电路系统及其制造方法
公开(公告)号：US08642475B2
公开(公告)日：2014-02-04
申请号：US12975327
申请日：2010-12-21
申请人： Xiang Hu , Helen Wang , Arifuzzaman (Arif) Sheikh , Habib Hichri , Richard Wise
发明人： Xiang Hu , Helen Wang , Arifuzzaman (Arif) Sheikh , Habib Hichri , Richard Wise
IPC分类号： H01L21/311
CPC分类号： H01L21/31138 , H01L21/32139
摘要： A method of manufacturing an integrated circuit system includes: providing a substrate; forming a polysilicon layer over the substrate; forming an anti-reflective coating layer over the polysilicon layer; etching an anti-reflective coating pattern into the anti-reflective coating layer leaving an anti-reflective coating residue over the polysilicon layer; and etching the anti-reflective coating residue with an etchant gas mixture comprising hydrogen bromide, chlorine, and oxygen to remove the anti-reflective coating residue for mitigating the formation of a polysilicon protrusion.
摘要翻译：集成电路系统的制造方法包括：提供基板; 在衬底上形成多晶硅层; 在所述多晶硅层上形成抗反射涂层; 将抗反射涂层图案蚀刻到抗反射涂层中，在多晶硅层上留下抗反射涂层残留物; 以及用包括溴化氢，氯和氧的蚀刻剂气体混合物蚀刻抗反射涂层残余物以除去抗反射涂层残余物以减轻多晶硅突起的形成。

6. 发明申请

US20120178241A1 CONDUCTIVE METAL AND DIFFUSION BARRIER SEED COMPOSITIONS, AND METHODS OF USE IN SEMICONDUCTOR AND INTERLEVEL DIELECTRIC SUBSTRATES 有权
标题翻译：导电金属和扩散阻挡物种子组合物，以及在半导体和交替电介质基板中的使用方法
公开(公告)号：US20120178241A1
公开(公告)日：2012-07-12
申请号：US12986266
申请日：2011-01-07
申请人： Kelly Malone , Habib Hichri
发明人： Kelly Malone , Habib Hichri
IPC分类号： H01L21/20 , B05D5/00 , H01B1/02
CPC分类号： H01B5/14 , H01B1/02 , H01B13/0026 , H01L21/283 , H01L21/76843 , H01L21/76871 , Y10T428/24999 , Y10T428/2982 , Y10T428/2989 , Y10T428/31663 , Y10T428/31678
摘要： A metal seed composition useful in seeding a metal diffusion barrier or conductive metal layer on a semiconductor or dielectric substrate, the composition comprising: a nanoscopic metal component that includes a metal useful as a metal diffusion barrier or conductive metal; an adhesive component for attaching said nanoscopic metal component on said semiconductor or dielectric substrate; and a linker component that links said nanoscopic metal component with said adhesive component. Semiconductor and dielectric substrates coated with the seed compositions, as well as methods for depositing the seed compositions, are also described.
摘要翻译：一种金属种子组合物，其可用于在半导体或电介质基底上接种金属扩散阻挡层或导电金属层，所述组合物包括：纳米金属组分，其包含可用作金属扩散阻挡层或导电金属的金属; 用于将所述纳米金属部件附着在所述半导体或电介质基板上的粘合部件; 以及将所述纳米金属组分与所述粘合剂组分连接的连接剂组分。还描述了涂覆有种子组合物的半导体和电介质基质以及沉积种子组合物的方法。

7. 发明申请

US20070111466A1 REDUCING DAMAGE TO ULK DIELECTRIC DURING CROSS-LINKED POLYMER REMOVAL 有权
标题翻译：在交联聚合物去除期间减少对ULK电介质的损伤
公开(公告)号：US20070111466A1
公开(公告)日：2007-05-17
申请号：US11164290
申请日：2005-11-17
申请人： Ronald DellaGuardia , Daniel Edelstein , Habib Hichri , Vincent McGahay
发明人： Ronald DellaGuardia , Daniel Edelstein , Habib Hichri , Vincent McGahay
IPC分类号： H01L21/76
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31133 , H01L21/76808
摘要： Methods are disclosed for reducing damage to an ultra-low dielectric constant (ULK) dielectric during removal of a planarizing layer such as a crosslinked polymer. The methods at least partially fill an opening with an at most lightly crosslinked polymer, followed by the planarizing layer. When the at most lightly crosslinked polymer and planarizing layer are removed, the at most lightly crosslinked polymer removal is easier than removal of the planarizing layer, i.e., crosslinked polymer, and does not damage the surrounding dielectric compared to removal chemistries used for the crosslinked polymer.
摘要翻译：公开了减少在去除平坦化层例如交联聚合物期间对超低介电常数（ULK）电介质的损伤的方法。该方法至少部分地用至少轻度交联的聚合物填充开口，随后是平坦化层。当除去至多轻度交联的聚合物和平坦化层时，与用于交联聚合物的去除化学物质相比，去除至多轻度交联的聚合物去除比去除平坦化层即交联聚合物更容易，并且不损坏周围的电介质。

8. 发明授权

US08822342B2 Method to reduce depth delta between dense and wide features in dual damascene structures 有权
标题翻译：减少双重镶嵌结构密集和宽特征之间深度三角洲的方法
公开(公告)号：US08822342B2
公开(公告)日：2014-09-02
申请号：US12981519
申请日：2010-12-30
申请人： Ravi Prakash Srivastava , Oluwafemi. O. Ogunsola , Craig Child , Muhammed Shafi Kurikka Valappil Pallachalil , Habib Hichri , Matthew Angyal , Hideshi Miyajima
发明人： Ravi Prakash Srivastava , Oluwafemi. O. Ogunsola , Craig Child , Muhammed Shafi Kurikka Valappil Pallachalil , Habib Hichri , Matthew Angyal , Hideshi Miyajima
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76813 , H01L21/31144 , H01L21/76808 , H01L21/76814 , H01L2221/1036 , H01L2221/1063
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.
摘要翻译：公开了一种形成装置的方法。该方法包括提供用具有第一和第二区域的电介质层制备的衬底。第一区域包括宽的特征，第二区域包括狭窄的特征。在宽和窄特征的底部之间存在深度增量。在基板上形成非保形层，并且在第一和第二区域中对宽且窄的沟槽进行排列。去除非保形层。去除非保形层减少了第一和第二区域中宽和窄特征的底部之间的深度增量。

9. 发明申请

US20120153474A1 INTEGRATED CIRCUIT SYSTEM WITH REDUCED POLYSILICON RESIDUE AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有减少多晶硅残留的集成电路系统及其制造方法
公开(公告)号：US20120153474A1
公开(公告)日：2012-06-21
申请号：US12975327
申请日：2010-12-21
申请人： Xiang Hu , Helen Wang , Arifuzzaman (Arif) Sheikh , Habib Hichri , Richard Wise
发明人： Xiang Hu , Helen Wang , Arifuzzaman (Arif) Sheikh , Habib Hichri , Richard Wise
IPC分类号： H01L21/283 , H01L29/49
CPC分类号： H01L21/31138 , H01L21/32139
摘要： A method of manufacturing an integrated circuit system includes: providing a substrate; forming a polysilicon layer over the substrate; forming an anti-reflective coating layer over the polysilicon layer; etching an anti-reflective coating pattern into the anti-reflective coating layer leaving an anti-reflective coating residue over the polysilicon layer; and etching the anti-reflective coating residue with an etchant gas mixture comprising hydrogen bromide, chlorine, and oxygen to remove the anti-reflective coating residue for mitigating the formation of a polysilicon protrusion.
摘要翻译：集成电路系统的制造方法包括：提供基板; 在衬底上形成多晶硅层; 在所述多晶硅层上形成抗反射涂层; 将抗反射涂层图案蚀刻到抗反射涂层中，在多晶硅层上留下抗反射涂层残留物; 以及用包括溴化氢，氯和氧的蚀刻剂气体混合物蚀刻抗反射涂层残余物以除去抗反射涂层残余物以减轻多晶硅突起的形成。

10. 发明授权

US07645621B2 Optical inspection methods 失效
标题翻译：光学检测方法
公开(公告)号：US07645621B2
公开(公告)日：2010-01-12
申请号：US11872900
申请日：2007-10-16
申请人： Colin Brodsky , Mary Jane Brodsky , Sean Burns , Habib Hichri
发明人： Colin Brodsky , Mary Jane Brodsky , Sean Burns , Habib Hichri
IPC分类号： H01L21/66 , G01R31/26 , G01N21/00 , G01C5/00
CPC分类号： G01N21/956 , H01L22/20
摘要： Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.
摘要翻译：检验方法一种方法包括将光学阻挡层直接粘附到半导体工艺晶片上并与半导体工艺晶片直接机械接触，所述阻挡层对于一定波长的光的范围基本上是不透明的; 在阻挡层上施加至少一层; 并且在光学上至少检测至少一个波长的至少一个检查区域，所述阻挡层基本上延伸遍及所述检查区域。一种检查方法，包括将光吸收层粘附到半导体处理晶片，其中吸收层被配置为基本上吸收一定范围的光的波长; 在吸收层上施加至少一层; 并且在光学上检查至少一个波长的处理晶片的至少一个检查区域。如果存在缺陷，则包括确定光致抗蚀剂层内是否存在缺陷以及改变半导体制造工艺以防止缺陷的制造方法。

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