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1. 发明授权

US08822342B2 Method to reduce depth delta between dense and wide features in dual damascene structures 有权
标题翻译：减少双重镶嵌结构密集和宽特征之间深度三角洲的方法
公开(公告)号：US08822342B2
公开(公告)日：2014-09-02
申请号：US12981519
申请日：2010-12-30
申请人： Ravi Prakash Srivastava , Oluwafemi. O. Ogunsola , Craig Child , Muhammed Shafi Kurikka Valappil Pallachalil , Habib Hichri , Matthew Angyal , Hideshi Miyajima
发明人： Ravi Prakash Srivastava , Oluwafemi. O. Ogunsola , Craig Child , Muhammed Shafi Kurikka Valappil Pallachalil , Habib Hichri , Matthew Angyal , Hideshi Miyajima
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76813 , H01L21/31144 , H01L21/76808 , H01L21/76814 , H01L2221/1036 , H01L2221/1063
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.
摘要翻译：公开了一种形成装置的方法。该方法包括提供用具有第一和第二区域的电介质层制备的衬底。第一区域包括宽的特征，第二区域包括狭窄的特征。在宽和窄特征的底部之间存在深度增量。在基板上形成非保形层，并且在第一和第二区域中对宽且窄的沟槽进行排列。去除非保形层。去除非保形层减少了第一和第二区域中宽和窄特征的底部之间的深度增量。

2. 发明申请

US20120168957A1 METHOD TO REDUCE DEPTH DELTA BETWEEN DENSE AND WIDE FEATURES IN DUAL DAMASCENE STRUCTURES 有权
标题翻译：降低DASASCENE结构中DENSE和WIDE特征之间深度差的方法
公开(公告)号：US20120168957A1
公开(公告)日：2012-07-05
申请号：US12981519
申请日：2010-12-30
申请人： Ravi Prakash SRIVASTAVA , Oluwafemi O. OGUNSOLA , Craig CHILD , Muhammed Shafi Kurikka Valappil PALLACHALIL , Habib HICHRI , Matthew ANGYAL , Hideshi MIYAJIMA
发明人： Ravi Prakash SRIVASTAVA , Oluwafemi O. OGUNSOLA , Craig CHILD , Muhammed Shafi Kurikka Valappil PALLACHALIL , Habib HICHRI , Matthew ANGYAL , Hideshi MIYAJIMA
IPC分类号： H01L23/48 , H01L21/31 , H01L21/28
CPC分类号： H01L21/76813 , H01L21/31144 , H01L21/76808 , H01L21/76814 , H01L2221/1036 , H01L2221/1063
摘要： A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.
摘要翻译：公开了一种形成装置的方法。该方法包括提供用具有第一和第二区域的电介质层制备的衬底。第一区域包括宽的特征，第二区域包括狭窄的特征。在宽和窄特征的底部之间存在深度增量。在基板上形成非保形层，并且在第一和第二区域中对宽且窄的沟槽进行排列。去除非保形层。去除非保形层减少了第一和第二区域中宽和窄特征的底部之间的深度增量。

3. 发明授权

US07325225B2 Method and apparatus for reducing OPC model errors 失效
标题翻译：减少OPC模型误差的方法和装置
公开(公告)号：US07325225B2
公开(公告)日：2008-01-29
申请号：US11243933
申请日：2005-10-05
申请人： Yasushi Tanaka , Masahiro Inohara , Matthew Angyal
发明人： Yasushi Tanaka , Masahiro Inohara , Matthew Angyal
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68
摘要： It is important to assess and reduce errors that arise in mask correction techniques such as optical proximity correction. A preliminary mask is obtained using an OPC model. An etched wafer is created from the preliminary mask using lithography, and first and second critical dimensions (CD) are measured on the wafer and. An edge placement error (EPE) is determined that corresponds to a difference between a measured value and a desired value of the second CD. These steps are repeated for a plurality of different values of the first CD, and of for each of the values of, the measured value of the second CD is correlated with its corresponding value on the mask as predicted by the OPC model. Δ difference ΔCD is obtained between the difference of the mask CDs calculated by interpolation of wafer CD measurements and by OPC model predictions and is transformed into an OPC model error.
摘要翻译：重要的是评估和减少在诸如光学邻近校正的掩模校正技术中出现的错误。使用OPC模型获得初步掩模。使用光刻从初步掩模创建蚀刻的晶片，并且在晶片上测量第一和第二临界尺寸（CD）。确定对应于测量值和第二CD的期望值之间的差的边缘放置误差（EPE）。对于第一CD的多个不同值重复这些步骤，并且对于每个值，第二CD的测量值与由OPC模型预测的掩模上的对应值相关。在通过晶片CD测量的插值和OPC模型预测计算出的掩模CD的差异之间获得差值DeltaCD，并将其转换为OPC模型误差。

4. 发明申请

US20110037143A1 Semiconductor Device Using An Aluminum Interconnect To Form Through-Silicon Vias 失效
标题翻译：使用铝互连形成通硅通孔的半导体器件
公开(公告)号：US20110037143A1
公开(公告)日：2011-02-17
申请号：US12539105
申请日：2009-08-11
申请人： Kevin S. Petrarca , Matthew Angyal , Lawrence A. Clevenger , Carl Radens , Brian C. Sapp
发明人： Kevin S. Petrarca , Matthew Angyal , Lawrence A. Clevenger , Carl Radens , Brian C. Sapp
IPC分类号： H01L29/92 , H01L23/48 , H01L21/02 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/76895 , H01L23/481 , H01L23/5222 , H01L28/60 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TV to other BEOL interconnects.
摘要翻译：线的后端（BEOL）的铝横向互连用于在形成于硅衬底中的半导体芯片中限定穿硅通孔的x和y尺寸。 TSV包括形成在基板的表面上的一个或多个铝环，以及基板中的深沟槽，其直径由铝环的直径决定。环也可以设置有可以形成电容器的导电带。带子也可用于提供电视与其他BEOL互连的连接。

5. 发明申请

US20050086615A1 Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures 失效
标题翻译：用于对片上互连结构进行建模和分析的计算机辅助设计方法和装置
公开(公告)号：US20050086615A1
公开(公告)日：2005-04-21
申请号：US10690238
申请日：2003-10-21
申请人： Minakshisundaran Anand , Matthew Angyal , Alina Deutsch , Ibrahim Elfadel , Gerard Kopcsay , Barry Rubin , Howard Smith
发明人： Minakshisundaran Anand , Matthew Angyal , Alina Deutsch , Ibrahim Elfadel , Gerard Kopcsay , Barry Rubin , Howard Smith
IPC分类号： G06F9/455 , G06F17/50 , G06F19/00 , G06G7/62
CPC分类号： G06F17/5036
摘要： A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.
摘要翻译：计算机辅助设计（CAD）系统。模板生成引擎从互连配置文件生成模板。场解算器从模板生成高频无源元件关系。电路构建器从器件技术模型和高频无源元件关系生成电路描述文件。可以为大范围的灵敏度分析生成参数化电路描述模型。模拟器模拟来自电路描述文件的传输线模型的电路响应。互连配置文件可以由接收来自设计者的过程描述数据的几何和材料定义模块生成。

6. 发明授权

US08350359B2 Semiconductor device using an aluminum interconnect to form through-silicon vias 失效
标题翻译：使用铝互连的半导体器件形成硅通孔
公开(公告)号：US08350359B2
公开(公告)日：2013-01-08
申请号：US12539105
申请日：2009-08-11
申请人： Kevin S. Petrarca , Matthew Angyal , Lawrence A. Clevenger , Carl Radens , Brian C. Sapp
发明人： Kevin S. Petrarca , Matthew Angyal , Lawrence A. Clevenger , Carl Radens , Brian C. Sapp
IPC分类号： H01L21/02 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/76895 , H01L23/481 , H01L23/5222 , H01L28/60 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TSV to other BEOL interconnects.
摘要翻译：线的后端（BEOL）的铝横向互连用于在形成于硅衬底中的半导体芯片中限定穿硅通孔的x和y尺寸。 TSV包括形成在基板的表面上的一个或多个铝环，以及基板中的深沟槽，其直径由铝环的直径决定。环也可以设置有可以形成电容器的导电带。带也可用于提供TSV与其他BEOL互连的连接。

7. 发明申请

US20070174796A1 Deflection analysis system and method for circuit design 失效
标题翻译：偏转分析系统及电路设计方法
公开(公告)号：US20070174796A1
公开(公告)日：2007-07-26
申请号：US11336524
申请日：2006-01-20
申请人： Matthew Angyal , Giovanni Fiorenza , Habib Hichri , Andrew Lu , Dale McHerron , Conal Murray
发明人： Matthew Angyal , Giovanni Fiorenza , Habib Hichri , Andrew Lu , Dale McHerron , Conal Murray
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.
摘要翻译：用于分析电路设计的系统，方法和计算机程序产品提供将电路设计离散成一系列像素。确定每个像素的至少一个构成材料的一部分。还为每个像素确定偏转。该偏转基于像素的平面化，并且在利用包括至少一个构成材料的分数的算法的同时进行计算。可以映射和评估一系列像素的一系列偏转。

8. 发明申请

US20070079278A1 Method and apparatus for reducing OPC model errors 失效
标题翻译：减少OPC模型误差的方法和装置
公开(公告)号：US20070079278A1
公开(公告)日：2007-04-05
申请号：US11243933
申请日：2005-10-05
申请人： Yasushi Tanaka , Masahiro Inohara , Matthew Angyal
发明人： Yasushi Tanaka , Masahiro Inohara , Matthew Angyal
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68
摘要： A method is provided of accessing model error in an optical proximity correction (OPC) model. The method begins by obtaining a preliminary mask using an OPC model, creating an etched wafer from the preliminary mask using lithography, and measuring a specified critical dimension (CD) on the wafer and a second CD on the wafer. An edge placement error (EPE) is determined that corresponds to a difference between a measured value of the second CD on the wafer and a desired value of the second CD on the wafer. The aforementioned steps are repeated for a plurality of different values of the specified CD to obtain an EPE for each of the different values of the specified CD. For each of the plurality of values of the specified CD, a measured value of a second CD on the wafer is correlated with a corresponding value of the second CD on the mask. For each of the plurality of values of the specified CD, the measured value of the second CD on the wafer is correlated with its corresponding value of the second CD on the mask as predicted by the OPC model. For each of the immediately preceding correlations that are obtained, and at a selected measured value of the second CD on the wafer, a difference Δ is obtained between the difference of the mask CDs calculated by interpolation of wafer CD measurements and by OPC model predictions. Each value of Δ is transformed into an OPC model error that each correspond to a particular value of the specified CD.
摘要翻译：提供了一种访问光学邻近校正（OPC）模型中的模型误差的方法。该方法开始于使用OPC模型获得初步掩模，使用光刻从初步掩模创建蚀刻晶片，并测量晶片上的指定临界尺寸（CD）和晶片上的第二CD。确定对应于晶片上的第二CD的测量值与晶片上的第二CD的期望值之间的差异的边缘放置误差（EPE）。针对指定CD的多个不同值重复上述步骤，以获得指定CD的每个不同值的EPE。对于指定CD的多个值中的每一个，晶片上的第二CD的测量值与掩模上的第二CD的相应值相关。对于指定CD的多个值中的每一个，晶片上的第二CD的测量值与由OPC模型预测的掩模上的第二CD的对应值相关。对于所获得的每个先前相关性，并且在晶片上的第二CD的选定测量值处，通过硅片CD测量的插值和通过OPC模型预测计算出的掩模CD的差异获得差值Delta。 Delta的每个值被转换成OPC模型错误，每个对应于指定CD的特定值。

9. 发明申请

US20060161412A1 Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertainty 失效
公开(公告)号：US20060161412A1
公开(公告)日：2006-07-20
申请号：US11037531
申请日：2005-01-18
申请人： Matthew Angyal , Alina Deutsch , Ibrahim Elfadel , Zhichao Zhang
发明人： Matthew Angyal , Alina Deutsch , Ibrahim Elfadel , Zhichao Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Techniques are disclosed for determination of parameter variability for one or more given interconnects of a plurality of interconnects in a simulated semiconductor circuit. The simulated semiconductor circuit is defined at least in part by a plurality of input parameters. From a distribution of first values of a given input parameter, a plurality of the first values are determined to use when calculating a corresponding plurality of second values for each of one or more output parameters. By using at least the determined plurality of first values for the given input parameter and selected values for other input parameters in the plurality of input parameters, the corresponding plurality of second values are calculated for each of the one or more output parameters. The one or more output parameters correspond to the one or more given interconnects. Each of the second values corresponds to one of the determined plurality of first values.

10. 发明申请

US20050242414A1 LOW-K INTERLEVEL DIELECTRIC LAYER (ILD) AND METHOD 失效
标题翻译： LOW-K交替介质层（ILD）和方法
公开(公告)号：US20050242414A1
公开(公告)日：2005-11-03
申请号：US10709320
申请日：2004-04-28
申请人： Matthew Angyal , Edward Barth , Sanjit Das , Charles Davis , Habib Hichri , William Landers , Jia Lee
发明人： Matthew Angyal , Edward Barth , Sanjit Das , Charles Davis , Habib Hichri , William Landers , Jia Lee
IPC分类号： H01L23/58
CPC分类号： H01L23/53295 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02362 , H01L21/31633 , H01L21/76829 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%-10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.
摘要翻译：层间电介质层（ILD）包括低k电介质层; 以及在压电应力下沉积在电介质层顶上的低k电介质膜。电介质层包括低k材料，例如有机硅玻璃（OSG）或SiCOH材料。电介质膜的厚度为电介质层厚度的2％-10％，与电介质层具有相似的化学成分，但具有与电介质层不同的形态。通过改变用于沉积低k电介质层的工艺，在介电层沉积的结束处或在其附近的压应力下沉积电介质膜。

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