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1. 发明授权

US10902115B2 Neuromorphic system for authorized user detection 有权
公开(公告)号：US10902115B2
公开(公告)日：2021-01-26
申请号：US16380687
申请日：2019-04-10
申请人： HRL Laboratories, LLC
发明人： Richard J. Patrick , Nigel D. Stepp , Vincent De Sapio , Jose Cruz-Albrecht , John Richard Haley, Jr. , Thomas M. Trostel
IPC分类号： G06F21/55 , G06N3/08
摘要： Described is neuromorphic system for authorized user detection. The system includes a client device comprising a plurality of sensor types providing streaming sensor data and one or more processors. The one or more processors include an input processing component and an output processing component. A neuromorphic electronic component is embedded in or on the client device for continuously monitoring the streaming sensor data and generating out-spikes based on the streaming sensor data. Further, the output processing component classifies the streaming sensor data based on the out-spikes to detect an anomalous signal and classify the anomalous signal.

2. 发明授权

US09843339B1 Asynchronous pulse domain to synchronous digital domain converter 有权
公开(公告)号：US09843339B1
公开(公告)日：2017-12-12
申请号：US15248358
申请日：2016-08-26
申请人： HRL Laboratories, LLC
发明人： Yen-Cheng Kuan , Randall White , Zhiwei A. Xu , Donald A. Hitko , Peter Petre , Jose Cruz-Albrecht , Alan E. Reamon
IPC分类号： H03M1/12 , H03M1/10 , G06F1/12 , G06F1/04
CPC分类号： G06F1/04 , G06F1/12
摘要： An asynchronous pulse domain to synchronous digital domain converter for converting pulse domain signals in an input asynchronous pulse domain data stream to synchronous digital domain signals in a data output stream. The converter comprises a plurality of counters arranged in a ring configuration with only one counter in the ring being responsive at any given time to positive and negative going pulses in the input asynchronous pulse domain data stream, each counter, when so responsive, counting a number of time units between either (i) a positive going pulse and an immediately following negative going pulse or (ii) a negative going pulse and an immediately following positive going pulse, the counts of the counters when so responsive being synchronously converted to synchronous digital domain signals in the data output stream. The disclosed asynchronous pulse domain to synchronous digital domain converter can be used with spike domain signals if desired.

3. 发明授权

US09484918B1 Dual edge pulse de-multiplexer with equalized path delay 有权
标题翻译：具有均衡路径延迟的双边沿脉冲解复用器
公开(公告)号：US09484918B1
公开(公告)日：2016-11-01
申请号：US14834837
申请日：2015-08-25
申请人： HRL LABORATORIES, LLC
发明人： Yen-Cheng Kuan , Ining Ku , Zhiwei A. Xu , Susan L. Morton , Donald A. Hitko , Peter Petre , Jose Cruz-Albrecht , Alan E. Reamon
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： H03K19/00369 , H01Q3/26 , H01Q3/2682 , H03K3/86 , H03K19/0016 , H04B7/0617 , H04B7/0671
摘要： A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.
摘要翻译：脉冲域1至2N解复用器具有（i）一对N级计数器，每个N级计数器响应于脉冲域中的输入脉冲序列，其中一个计数器响应于输入脉冲串中的脉冲的前沿，另一个计数器响应输入脉冲串中的脉冲的后沿，以及（ii）响应于该对计数器计数的状态的控制逻辑，包括2N个门装置的控制逻辑，2N个门结构产生脉冲域1至2N解复用器的输出信号。

4. 发明授权

US09082075B1 Combined spike domain and pulse domain signal processing 有权
标题翻译：组合尖峰域和脉冲域信号处理
公开(公告)号：US09082075B1
公开(公告)日：2015-07-14
申请号：US14032082
申请日：2013-09-19
申请人： HRL Laboratories, LLC
发明人： Jose Cruz-Albrecht , Peter Petre
IPC分类号： H03M1/66 , G06N3/02 , H03M1/10
CPC分类号： G06N3/02 , G06N3/049 , G06N3/063 , H03M1/1023
摘要： A method of, and apparatus for, the processing analog data. The method includes the steps of: time encoding the analog data; setting weighting factors in an array of 1-bit DACs for processing the time encoded analog data; summing and filtering outputs of the array of 1-bit DACs; time encoding the filtered outputs of the outputs of the array of 1-bit DACs; and coupling the time encoded filtered outputs and analog input data into inputs of the array of 1-bit DACs.
摘要翻译：用于处理模拟数据的方法和装置。该方法包括以下步骤：对模拟数据进行时间编码; 设置用于处理时间编码的模拟数据的1位DAC阵列中的加权因子; 对1位DAC阵列的输出进行求和和滤波; 对1位DAC阵列的输出的滤波输出进行时间编码; 并将时间编码的滤波输出和模拟输入数据耦合到1位DAC阵列的输入端。

5. 发明授权

US11270411B1 Efficient hardware design and implementation of image interpolation and resizing for image processing pipeline 有权
公开(公告)号：US11270411B1
公开(公告)日：2022-03-08
申请号：US16369779
申请日：2019-03-29
申请人： HRL Laboratories, LLC
发明人： Austin F. Garrido , Shankar R. Rao , Jose Cruz-Albrecht , Timothy J. Derosier
IPC分类号： G06T3/40 , G06F1/324 , G06T1/60
摘要： A system for real time bilinear interpolation includes a bilinear interpolation module capable of: generating pixel addresses for original image pixels of an original image needed for performing bilinear interpolation of the original image to form a resized image, wherein the generated pixel addresses assume all the original image pixels of the original image are accessible, and performing bilinear interpolation, and a pixel smart memory module capable: of sequentially receiving original image pixel rows of the original image an original image pixel row a time, predicting which original image pixel rows are needed for performing bilinear interpolation, storing only the needed sequentially received original image pixel rows in a memory, decoding the generated pixel addresses to form decoded addresses to access the needed original image pixel rows stored in the memory, and sending the needed original image pixel rows to the bilinear interpolation module for performing bilinear interpolation.

6. 发明申请

US20190303568A1 NEUROMORPHIC SYSTEM FOR AUTHORIZED USER DETECTION 审中-公开
公开(公告)号：US20190303568A1
公开(公告)日：2019-10-03
申请号：US16380687
申请日：2019-04-10
申请人： HRL Laboratories, LLC
发明人： Richard J. Patrick , Nigel D. Stepp , Vincent De Sapio , Jose Cruz-Albrecht , John Richard Haley , Thomas M. Trostel
IPC分类号： G06F21/55 , G06N3/08
摘要： Described is neuromorphic system for authorized user detection. The system includes a client device comprising a plurality of sensor types providing streaming sensor data and one or more processors. The one or more processors include an input processing component and an output processing component. A neuromorphic electronic component is embedded in or on the client device for continuously monitoring the streaming sensor data and generating out-spikes based on the streaming sensor data. Further, the output processing component classifies the streaming sensor data based on the out-spikes to detect an anomalous signal and classify the anomalous signal.

7. 发明申请

US20190230107A1 SYSTEM FOR CONTINUOUS VALIDATION AND THREAT PROTECTION OF MOBILE APPLICATIONS 审中-公开
公开(公告)号：US20190230107A1
公开(公告)日：2019-07-25
申请号：US16199128
申请日：2018-11-23
申请人： HRL Laboratories, LLC
发明人： Vincent De Sapio , Hyun (Tiffany) J. Kim , Kyungnam Kim , Nigel D. Stepp , Kang-Yu Ni , Jose Cruz-Albrecht , Braden Mailloux
IPC分类号： H04L29/06 , H04W12/12 , G06F21/55 , H04L12/24 , G06N3/063
摘要： Described is a low power system for mobile devices that provides continuous, behavior-based security validation of mobile device applications using neuromorphic hardware. A mobile device comprises a neuromorphic hardware component that runs on the mobile device for continuously monitoring time series related to individual mobile device application behaviors, detecting and classifying pattern anomalies associated with a known malware threat in the time series related to individual mobile device application behaviors, and generating an alert related to the known malware threat. The mobile device identifies pattern anomalies in dependency relationships of mobile device inter-application and intra-applications communications, detects pattern anomalies associated with new malware threats, and isolates a mobile device application having a risk of malware above a predetermined threshold relative to a risk management policy.

8. 发明授权

US10147035B2 Neural integrated circuit with biological behaviors 有权
公开(公告)号：US10147035B2
公开(公告)日：2018-12-04
申请号：US15199800
申请日：2016-06-30
申请人： HRL Laboratories, LLC
发明人： Jose Cruz-Albrecht , Timothy Derosier , Narayan Srinivasa
IPC分类号： G06F15/00 , G06N3/063 , G06F7/50 , G06F7/523 , G06F7/48
摘要： A circuit for emulating the behavior of biological neural circuits, the circuit including a plurality of nodes wherein each node comprises a neuron circuit, a time multiplexed synapse circuit coupled to an input of the neuron circuit, a time multiplexed short term plasticity (STP) circuit coupled to an input of the node and to the synapse circuit, a time multiplexed Spike Timing Dependent Plasticity (STDP) circuit coupled to the input of the node and to the synapse circuit, an output of the node coupled to the neuron circuit; and an interconnect fabric coupled between the plurality of nodes for providing coupling from the output of any node of the plurality of nodes to any input of any other node of the plurality of nodes.

9. 发明授权

US09824311B1 Asynchronous pulse domain processor with adaptive circuit and reconfigurable routing 有权
公开(公告)号：US09824311B1
公开(公告)日：2017-11-21
申请号：US14259314
申请日：2014-04-23
申请人： HRL Laboratories, LLC
发明人： Jose Cruz-Albrecht , Peter Petre , Randall White
IPC分类号： G06F15/18 , G06N3/08
CPC分类号： G06N3/08 , G06N3/0445 , G06N3/049 , G06N3/0635
摘要： A liquid state machine pulse domain neural processor circuit comprising an asynchronous input filter circuit provided for, at any given time, receiving a series of analog input signals and generating in response a set of time-encoded values that depend on the series of analog input signals received at said given time and before said given time; and an asynchronous trainable readout map circuit for transforming at least a portion of said set of time encoded values into output signals.

10. 发明申请

US20160239947A1 SPIKE DOMAIN CONVOLUTION CIRCUIT 有权
标题翻译： SPIKE域转换电路
公开(公告)号：US20160239947A1
公开(公告)日：2016-08-18
申请号：US15043478
申请日：2016-02-12
申请人： HRL Laboratories, LLC
发明人： Jose Cruz-Albrecht , Michael W. Yung , Narayan Srinivasa
IPC分类号： G06T5/20 , H03M1/66 , H03D7/14
CPC分类号： G06T5/20
摘要： A convolution circuit includes: a plurality of input oscillators, each configured to: receive a corresponding analog input signal of a plurality of analog input signals; and output a corresponding spiking signal of a plurality of spiking signals, the corresponding spiking signal having a spiking rate in accordance with a magnitude of the corresponding analog input signal; a plurality of 1-bit DACs, each of the 1-bit DACs being configured to: receive the corresponding spiking signal of the plurality of spiking signals from a corresponding one of the input oscillators; and receive a corresponding weight of a convolution kernel comprising a plurality of weights; output a corresponding weighted output of a plurality of weighted outputs in accordance with the corresponding spiking signal and the corresponding weight; and an output oscillator configured to generate an output spike signal in accordance with the plurality of weighted outputs from the plurality of 1-bit DACs.
摘要翻译：卷积电路包括：多个输入振荡器，每个输入振荡器被配置为：接收多个模拟输入信号的对应的模拟输入信号; 并输出多个尖峰信号的对应尖峰信号，相应的尖峰信号具有根据对应的模拟输入信号的大小的尖峰速率; 多个1位DAC，所述1位DAC中的每一个被配置为：从所述输入振荡器中的相应一个接收所述多个尖峰信号的对应尖峰信号; 并且接收包括多个权重的卷积核的相应权重; 根据相应的加标信号和相应的权重输出多个加权输出的对应加权输出; 以及输出振荡器，被配置为根据来自所述多个1位DAC的所述多个加权输出来产生输出尖峰信号。

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