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1. 发明授权

US10361731B2 Interleaved sigma delta modulator based SDR transmitter 有权
公开(公告)号：US10361731B2
公开(公告)日：2019-07-23
申请号：US15828106
申请日：2017-11-30
申请人： HRL Laboratories, LLC
发明人： Zhiwei A. Xu , Yen-Cheng Kuan , Cynthia D. Baringer , Hasan Sharifi , James Chingwei Li , Donald A. Hitko
IPC分类号： H04B1/04 , H03M3/00 , H03M7/16
摘要： A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.

2. 发明申请

US20190165820A1 INTERLEAVED SIGMA DELTA MODULATOR BASED SDR TRANSMITTER 审中-公开
公开(公告)号：US20190165820A1
公开(公告)日：2019-05-30
申请号：US15828106
申请日：2017-11-30
申请人： HRL Laboratories, LLC
发明人： Zhiwei A. Xu , Yen-Cheng Kuan , Cynthia D. Baringer , Hasan Sharifi , James Chingwei Li , Donald A. Hitko
IPC分类号： H04B1/04 , H03M3/00
CPC分类号： H04B1/04 , H03M3/502 , H03M7/165
摘要： A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.

3. 发明授权

US09662498B1 Scalable high-density wireless neuroelectric sensor and stimulator array 有权
公开(公告)号：US09662498B1
公开(公告)日：2017-05-30
申请号：US14669794
申请日：2015-03-26
申请人： HRL LABORATORIES LLC
发明人： Kyung-Ah Son , Jeong-Sun Moon , Zhiwei A. Xu , Brian N. Limketkai , Jongchan Kang , Tahir Hussain
IPC分类号： A61N1/00 , A61N1/36 , A61N1/372
CPC分类号： G01N33/4836 , A61B5/0478 , A61B5/6868 , A61B2562/0209 , A61B2562/028 , A61B2562/046 , A61N1/0531 , A61N1/36125 , A61N1/37229 , A61N1/3787 , C23C16/26 , C23C16/45525 , C23C16/56 , H01L21/02527 , H01L21/0262 , H01L21/042 , H01L21/044
摘要： A neuroelectric sensor and stimulator system includes a first antenna, a reader coupled to the first antenna for transmitting stimulation controls and power to a second antenna, and for receiving sensor data transmitted from the second antenna via the first antenna, and at least one neuroelectric sensor stimulator array including the second antenna, a rectifier coupled to the second antenna for extracting power transmitted from the first antenna, a controller coupled to the second antenna for decoding controls transmitted from the first antenna to the second antenna for the neuroelectric sensor stimulator array, a plurality of sensors, a multiplexer coupled to the controller and to the plurality of sensors for selecting a single sensor, and a plurality of stimulators coupled to the controller for stimulating neurons, wherein the rectifier, the controller, the plurality of sensors, the multiplexer, and the plurality of stimulators include graphene.

4. 发明授权

US09531571B2 Agile radio architecture 有权
标题翻译：敏捷无线电架构
公开(公告)号：US09531571B2
公开(公告)日：2016-12-27
申请号：US14144767
申请日：2013-12-31
申请人： HRL Laboratories, LLC
发明人： Zhiwei A. Xu , Yen-Cheng Kuan , James Chingwei Li , Donald A. Hitko , Joseph F. Jensen
IPC分类号： H04L25/00 , H04L25/08 , H03D7/14
CPC分类号： H04L25/08 , H03D7/1441 , H03D7/1458 , H04B1/0035
摘要： An agile transceiver including a receiver channel that includes an input, a coarse tracking filter coupled to the input, the coarse tracking filter having a set of at least two bandpass filters for filtering signals from the input into at least two coarse pass bands, a mixer coupled to an output of the coarse tracking filter, a selected local oscillator coupled to the mixer for mixing with the output of the coarse tracking filter and shifting a desired coarse pass band to near a base band, a fine tracking filter for filtering the shifted and desired coarse pass band to a fine pass band, and a band pass ΣΔ demodulator for converting signals in the fine pass band from analog into digital. The agile transceiver may include a corresponding transmitter channel.
摘要翻译：一种敏捷收发器，包括包括输入的接收器通道，耦合到输入的粗跟踪滤波器，粗跟踪滤波器具有一组至少两个带通滤波器，用于将来自输入的信号滤波成至少两个粗通带;混频器耦合到粗跟踪滤波器的输出，耦合到混频器的选定的本地振荡器，用于与粗跟踪滤波器的输出混合并将期望的粗通带移位到基带附近;精细跟踪滤波器，用于滤波偏移和期望的粗通带到细通带，以及带通ΣΔ解调器，用于将细通带中的信号从模拟转换成数字。敏捷收发器可以包括相应的发射机信道。

5. 发明授权

US10340889B1 Low noise non-foster circuit 有权
公开(公告)号：US10340889B1
公开(公告)日：2019-07-02
申请号：US15275151
申请日：2016-09-23
申请人： HRL Laboratories, LLC
发明人： Zhiwei A. Xu , Carson R. White , Jonathan J. Lynch
IPC分类号： H01Q1/52 , H03H11/04 , H03H11/28
摘要： A method of and an apparatus for reducing noise in a non-Foster circuit having at least a pair of cross coupled transistor devices, each transistor device of the pair of cross coupled transistor devices having a pair of current carrying electrodes. The method and apparatus involves coupling inductors with each pair of the current carrying electrodes of each of the cross-coupled transistor devices in the non-Foster circuit, the inductors also being coupled with voltage and/or current sources associated with or coupled to the non-Foster circuit. The nominal values of the inductors are selected to provide a load asymmetry, so that the load inductor in the input side of the non-Foster circuit has a larger inductance than the load inductor at the output side of non-Foster circuit.

6. 发明授权

US09880148B1 Scalable high-density wireless neuroelectric sensor and stimulator array 有权
公开(公告)号：US09880148B1
公开(公告)日：2018-01-30
申请号：US15478129
申请日：2017-04-03
申请人： HRL Laboratories, LLC
发明人： Kyung-Ah Son , Jeong-Sun Moon , Zhiwei A. Xu , Brian N. Limketkai , Jongchan Kang , Tahir Hussain
IPC分类号： A61N1/00 , G01N33/483 , C23C16/455 , C23C16/56 , C23C16/26 , H01L21/04 , H01L21/02
CPC分类号： G01N33/4836 , A61B5/0478 , A61B5/6868 , A61B2562/0209 , A61B2562/028 , A61B2562/046 , A61N1/0531 , A61N1/36125 , A61N1/37229 , A61N1/3787 , C23C16/26 , C23C16/45525 , C23C16/56 , H01L21/02527 , H01L21/0262 , H01L21/042 , H01L21/044
摘要： A neuroelectric sensor and stimulator system includes a first antenna, a reader coupled to the first antenna for transmitting stimulation controls and power to a second antenna, and for receiving sensor data transmitted from the second antenna via the first antenna, and at least one neuroelectric sensor stimulator array including the second antenna, a rectifier coupled to the second antenna for extracting power transmitted from the first antenna, a controller coupled to the second antenna for decoding controls transmitted from the first antenna to the second antenna for the neuroelectric sensor stimulator array, a plurality of sensors, a multiplexer coupled to the controller and to the plurality of sensors for selecting a single sensor, and a plurality of stimulators coupled to the controller for stimulating neurons, wherein the rectifier, the controller, the plurality of sensors, the multiplexer, and the plurality of stimulators include graphene.

7. 发明授权

US09843339B1 Asynchronous pulse domain to synchronous digital domain converter 有权
公开(公告)号：US09843339B1
公开(公告)日：2017-12-12
申请号：US15248358
申请日：2016-08-26
申请人： HRL Laboratories, LLC
发明人： Yen-Cheng Kuan , Randall White , Zhiwei A. Xu , Donald A. Hitko , Peter Petre , Jose Cruz-Albrecht , Alan E. Reamon
IPC分类号： H03M1/12 , H03M1/10 , G06F1/12 , G06F1/04
CPC分类号： G06F1/04 , G06F1/12
摘要： An asynchronous pulse domain to synchronous digital domain converter for converting pulse domain signals in an input asynchronous pulse domain data stream to synchronous digital domain signals in a data output stream. The converter comprises a plurality of counters arranged in a ring configuration with only one counter in the ring being responsive at any given time to positive and negative going pulses in the input asynchronous pulse domain data stream, each counter, when so responsive, counting a number of time units between either (i) a positive going pulse and an immediately following negative going pulse or (ii) a negative going pulse and an immediately following positive going pulse, the counts of the counters when so responsive being synchronously converted to synchronous digital domain signals in the data output stream. The disclosed asynchronous pulse domain to synchronous digital domain converter can be used with spike domain signals if desired.

8. 发明授权

US09621183B2 Interleaved Δ-Σ modulator 有权
公开(公告)号：US09621183B2
公开(公告)日：2017-04-11
申请号：US14745354
申请日：2015-06-19
申请人： HRL LABORATORIES LLC
发明人： Cynthia D. Baringer , Zhiwei A. Xu , Peter Petre , Donald A. Hitko , Albert Cosand
IPC分类号： H03M3/00 , H03M1/06
CPC分类号： H03M3/47 , H03M1/066 , H03M3/358 , H03M3/37 , H03M3/454 , H03M3/46
摘要： A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.

9. 发明授权

US09581681B2 Method and apparatus for processing coded aperture radar (CAR) signals 有权
标题翻译：编码孔径雷达（CAR）信号的处理方法和装置
公开(公告)号：US09581681B2
公开(公告)日：2017-02-28
申请号：US14561111
申请日：2014-12-04
申请人： HRL Laboratories, LLC
发明人： Jonathan J. Lynch , Zhiwei A. Xu , Yen-Cheng Kuan
IPC分类号： G01S13/72 , G01S7/28 , G01S7/02 , G01S13/02 , G01S13/34 , G01S13/44 , G01S13/536 , G01S7/35 , G01S13/88 , G01S13/93 , G01S13/94
CPC分类号： G01S7/2813 , G01S7/02 , G01S13/02 , G01S13/343 , G01S13/4418 , G01S13/4463 , G01S13/536 , G01S13/882 , G01S13/931 , G01S13/94 , G01S2007/356
摘要： A radar system in which Coded Aperture Radar processing is performed on received radar signals reflected by one or more objects in a field of view which reflect a transmitted signal which covers a field of view with K sweeps and each sweep including Q frequency changes. For Type II CAR, the transmitted signal also includes N modulated codes per frequency step. The received radar signals are modulated by a plurality of binary modulators the results of which are applied to a mixer. The output of the mixer, for one acquisition results in a set of Q·K (for Type I CAR) or Q·K·N (for Type II CAR) complex data samples, is distributed among a number of digital channels, each corresponding to a desired beam direction. For each channel, the complex digital samples are multiplied, sample by sample, by a complex signal mask that is different for each channel.
摘要翻译：一种雷达系统，其中在视场中由一个或多个物体反射的接收的雷达信号执行编码孔径雷达处理，其反映覆盖具有K个扫描的视场的发射信号，并且每个扫描包括Q个频率变化。对于II型CAR，发射信号还包括每个频率步长的N个调制码。所接收的雷达信号由多个二进制调制器调制，其结果应用于混频器。对于一次采集，混合器的输出导致一组Q·K（对于I型CAR）或Q·K·N（对于II型CAR）复数数据样本，分布在多个数字通道中，每个对应到期望的波束方向。对于每个通道，复数数字样本通过样本逐个乘以每个通道不同的复信号掩码。

10. 发明授权

US09484918B1 Dual edge pulse de-multiplexer with equalized path delay 有权
标题翻译：具有均衡路径延迟的双边沿脉冲解复用器
公开(公告)号：US09484918B1
公开(公告)日：2016-11-01
申请号：US14834837
申请日：2015-08-25
申请人： HRL LABORATORIES, LLC
发明人： Yen-Cheng Kuan , Ining Ku , Zhiwei A. Xu , Susan L. Morton , Donald A. Hitko , Peter Petre , Jose Cruz-Albrecht , Alan E. Reamon
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： H03K19/00369 , H01Q3/26 , H01Q3/2682 , H03K3/86 , H03K19/0016 , H04B7/0617 , H04B7/0671
摘要： A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.
摘要翻译：脉冲域1至2N解复用器具有（i）一对N级计数器，每个N级计数器响应于脉冲域中的输入脉冲序列，其中一个计数器响应于输入脉冲串中的脉冲的前沿，另一个计数器响应输入脉冲串中的脉冲的后沿，以及（ii）响应于该对计数器计数的状态的控制逻辑，包括2N个门装置的控制逻辑，2N个门结构产生脉冲域1至2N解复用器的输出信号。

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