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    • 3. 发明授权
    • Priority encoder with multiple match function for content addressable memories and methods for implementing the same
    • 具有多个匹配功能的优先编码器,用于内容可寻址存储器及其实现方法
    • US06392910B1
    • 2002-05-21
    • US09642253
    • 2000-08-17
    • Jason Edward PodaimaKenneth J. Schultz
    • Jason Edward PodaimaKenneth J. Schultz
    • G11C1500
    • G06F7/74G11C15/00G11C15/04G11C29/14G11C29/26G11C29/816G11C2029/2602
    • A priority resolver for use in a CAM circuit priority encoder is provided. The priority resolver includes one or more priority resolver sub-units. Each priority resolver sub-unit includes an local hit (pehit) generation circuitry. The local hit (pehit) generation circuitry is configured to generate pehit data. Also provided as part of a priority resolver sub-unit is a resolve processing circuit that is coupled to the local hit (pehit) generation circuitry. The resolve processing circuit is configured to receive the pehit data and an enable signal. Preferably, the resolve processing circuit includes input gating circuitry. An output differentiator and gating circuit is further provided as part of the priority resolver sub-unit and is configured to receive an output of the resolve processing circuit. In this embodiment, the priority resolver sub-unit is implemented in one or more stages of the priority resolver, and each stage is configured to include one or more priority resolver sub-units.
    • 提供了一种用于CAM电路优先级编码器的优先级解算器。 优先级解析器包括一个或多个优先级解析器子单元。 每个优先级解算器子单元包括本地命中(pehit)生成电路。 本地命中(pehit)生成电路被配置为生成pehit数据。 作为优先级解算器子单元的一部分还提供了一个耦合到本地命中(pehit)生成电路的解析处理电路。 解析处理电路被配置为接收pehit数据和使能信号。 优选地,解析处理电路包括输入选通电路。 进一步提供输出微分器和门控电路作为优先级解算器子单元的一部分,并且被配置为接收解析处理电路的输出。 在本实施例中,优先级解算器子单元在优先级解算器的一个或多个阶段中实现,并且每个级被配置为包括一个或多个优先级解算器子单元。
    • 5. 发明授权
    • Three port content addressable memory device and methods for implementing the same
    • 三端口内容可寻址存储器件及其实现方法
    • US06362990B1
    • 2002-03-26
    • US09654319
    • 2000-09-01
    • G. F. Randall GibsonFarhad ShafaiKenneth J. Schultz
    • G. F. Randall GibsonFarhad ShafaiKenneth J. Schultz
    • G11C1500
    • G11C29/816G11C8/16G11C15/00G11C15/04G11C29/14G11C2029/2602
    • A three-port content addressable memory (CAM) device and method thereof are provided. The three-port CAM device includes a CAM, a search control block, and a maintenance control block. The CAM is configured to store data. The search control block is arranged to receive search data and search control signals via a first port for searching the search data in the CAM. The search control block is further configured to perform search operations by accessing the CAM. The search operations are performed within search cycles with each search operation being performed over multiple clock cycles. In this configuration, more than one search operations are capable of being performed simultaneously over one or more clock cycles. Search results of the search operations are output via a second port. The maintenance control block is configured to perform read/write operations by reading or writing specified data in the CAM via a third port.
    • 提供三端口内容可寻址存储器(CAM)装置及其方法。 三端口CAM设备包括CAM,搜索控制块和维护控制块。 CAM配置为存储数据。 搜索控制块被布置成经由用于搜索CAM中的搜索数据的第一端口接收搜索数据和搜索控制信号。 搜索控制块还被配置为通过访问CAM来执行搜索操作。 搜索操作在搜索周期内进行,每个搜索操作在多个时钟周期内执行。 在该配置中,可以在一个或多个时钟周期上同时执行多于一个的搜索操作。 通过第二个端口输出搜索操作的搜索结果。 维护控制块被配置为通过经由第三端口读取或写入CAM中的指定数据来执行读/写操作。