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1. 发明申请

US20080191317A1 SELF-ALIGNED EPITAXIAL GROWTH OF SEMICONDUCTOR NANOWIRES 审中-公开
标题翻译：自对准的半导体纳米粒子的外延生长
公开(公告)号：US20080191317A1
公开(公告)日：2008-08-14
申请号：US11674453
申请日：2007-02-13
申请人： Guy Moshe Cohen , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
发明人： Guy Moshe Cohen , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/0665 , B82Y10/00 , C30B11/12 , C30B29/60 , H01L21/0237 , H01L21/02381 , H01L21/02521 , H01L21/02603 , H01L21/02639 , H01L21/02642 , H01L21/02645 , H01L21/02653 , H01L21/28525 , H01L29/0673 , H01L29/0676 , H01L2221/1094
摘要： Disclosed herein is a method of forming a nanostructure having nanowires by forming a mask with at least one opening on a surface of a substrate, to expose a portion of the surface of the substrate; depositing particles of a metal capable of catalyzing semiconductor nanowire growth on the exposed surface of the substrate by electroplating or electroless plating; and growing nanowires on the plated substrate with a precursor gas by a vapor-liquid-solid (VLS) process. Also disclosed is a nanostructure including nanowires prepared by the above method.
摘要翻译：本文公开了一种通过在衬底的表面上形成具有至少一个开口的掩模来形成具有纳米线的纳米结构的方法，以暴露衬底表面的一部分; 通过电镀或化学电镀将能够催化半导体纳米线生长的金属的颗粒沉积在基板的暴露表面上; 并通过气 - 液 - 固（VLS）工艺在具有前体气体的电镀衬底上生长纳米线。还公开了包括通过上述方法制备的纳米线的纳米结构。

2. 发明授权

US07785982B2 Structures containing electrodeposited germanium and methods for their fabrication 失效
标题翻译：含有电沉积锗的结构及其制造方法
公开(公告)号：US07785982B2
公开(公告)日：2010-08-31
申请号：US11620224
申请日：2007-01-05
申请人： Stephen W. Bedell , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw , Devendra K. Sadana , Katherine L. Saenger
发明人： Stephen W. Bedell , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/0237 , H01L21/02532 , H01L21/02628 , H01L21/02636 , H01L21/02639 , H01L21/28255 , H01L29/1054 , H01L29/78
摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
摘要翻译：提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。

3. 发明申请

US20090294989A1 FORMATION OF VERTICAL DEVICES BY ELECTROPLATING 有权
标题翻译：通过电镀形成垂直装置
公开(公告)号：US20090294989A1
公开(公告)日：2009-12-03
申请号：US12538782
申请日：2009-08-10
申请人： Hariklia Deligianni , Qiang Huang , John P. Hummel , Lubomyr T. Romankiw , Mary B. Rothwell
发明人： Hariklia Deligianni , Qiang Huang , John P. Hummel , Lubomyr T. Romankiw , Mary B. Rothwell
IPC分类号： H01L23/48
CPC分类号： H01L21/76879 , H01L21/2885 , Y10S205/925
摘要： The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.
摘要翻译：本发明涉及通过电镀形成垂直导电结构的方法。具体地，首先形成模板结构，其包括衬底，位于衬底表面上的离散金属接触焊盘，分立金属接触焊盘和衬底两者之间的级间电介质（ILD）层，以及金属通孔结构延伸穿过ILD层到分立的金属接触垫上。接下来，在模板结构中形成垂直通孔，其延伸穿过ILD层到分立的金属接触垫上。然后通过电镀在垂直通孔中形成垂直导电结构，电镀通过通过金属通孔结构将电镀电流施加到离散的金属接触焊盘来进行。优选地，模板结构包括多个分立的金属接触焊盘，多个金属通孔结构以及用于形成多个垂直导电结构的多个垂直通孔。

4. 发明授权

US08637849B2 Vertical nanowire FET devices 有权
标题翻译：垂直纳米线FET器件
公开(公告)号：US08637849B2
公开(公告)日：2014-01-28
申请号：US12984653
申请日：2011-01-05
申请人： Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
发明人： Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
IPC分类号： H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02521 , H01L21/02628 , H01L21/02639 , H01L29/0676 , H01L29/42392 , H01L29/66742 , H01L29/775 , H01L29/78642
摘要： A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode.
摘要翻译：形成在衬底上的垂直场效应晶体管（VFET），其上形成有导电底电极。在其上方形成由栅电极包围的底部电介质隔离层和栅介质层。以上是上隔离层。孔在电极之间延伸穿过。柱状垂直半导体纳米线（VSN）填充孔和顶部和底部电极之间。在VSN的相对端处的掺杂源极和漏极区域之间的VSN的中心区域中形成FET沟道。在底部电介质间隔层上方的VSN的外表面上形成的栅极电介质结构将VSN与栅电极分离。

5. 发明申请

US20130008798A1 ELECTRODEPOSITION METHODS OF GALLIUM AND GALLIUM ALLOY FILMS AND RELATED PHOTOVOLTAIC STRUCTURES 审中-公开
标题翻译：镓和镓合金膜的电沉积方法和相关的光伏结构
公开(公告)号：US20130008798A1
公开(公告)日：2013-01-10
申请号：US13604054
申请日：2012-09-05
申请人： Shafaat Ahmed , Hariklia Deligianni , Qiang Huang , Kathleen B. Reuter , Lubomyr T. Romankiw , Raman Vaidyanathan
发明人： Shafaat Ahmed , Hariklia Deligianni , Qiang Huang , Kathleen B. Reuter , Lubomyr T. Romankiw , Raman Vaidyanathan
IPC分类号： C25D5/10 , C25D5/50 , C25D5/48
CPC分类号： H01L31/0322 , C25D3/38 , C25D3/54 , C25D3/58 , C25D5/10 , C25D5/56 , C25D7/126 , H01L21/02568 , H01L21/02628 , H01L23/3738 , H01L31/0749 , H01L2224/73253 , Y02E10/541
摘要： Photovoltaic devices and methods for preparing a p-type semiconductor generally include electroplating a layer of gallium or a gallium alloy onto a conductive layer by contacting the conductive layer with a plating bath free of complexing agents including a gallium salt, methane sulfonic acid or sodium sulfate and an organic additive comprising at least one nitrogen atom and/or at least one sulfur atom, and a solvent; adjusting a pH of the solution to be less than 2.6 or greater than 12.6. The photovoltaic device includes an impurity in the p-type semiconductor layer selected from the group consisting of arsenic, antimony, bismuth, and mixtures thereof. Various photovoltaic precursor layers for forming CIS, CGS and CIGS p-type semiconductor structures can be formed by electroplating the gallium or gallium alloys in this manner. Also disclosed are processes for forming a thermal interface of gallium or a gallium alloy.
摘要翻译：用于制备p型半导体的光伏器件和方法通常包括通过使导电层与不含络合剂的镀浴接触将一层镓或镓合金电镀到导电层上，所述络合剂包括镓盐，甲磺酸或硫酸钠和包含至少一个氮原子和/或至少一个硫原子的有机添加剂和溶剂; 调节溶液的pH值小于2.6或大于12.6。光电器件包括选自砷，锑，铋及其混合物的p型半导体层中的杂质。可以通过以这种方式电镀镓或镓合金来形成用于形成CIS，CGS和CIGS p型半导体结构的各种光伏前体层。还公开了形成镓或镓合金的热界面的方法。

6. 发明授权

US07659200B2 Self-constrained anisotropic germanium nanostructure from electroplating 失效
标题翻译：电镀自限制各向异性锗纳米结构
公开(公告)号：US07659200B2
公开(公告)日：2010-02-09
申请号：US11620391
申请日：2007-01-05
申请人： Guy Cohen , Qiang Huang , Lubomyr T. Romankiw , Hariklia Deligianni
发明人： Guy Cohen , Qiang Huang , Lubomyr T. Romankiw , Hariklia Deligianni
IPC分类号： H01L21/302
CPC分类号： C25D3/54 , B82Y10/00 , C25D5/022 , C25D7/123 , H01L21/0237 , H01L21/02532 , H01L21/02603 , H01L21/02628 , H01L21/02639 , Y10S977/762
摘要： A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.
摘要翻译：提供包括锗的纳米结构，其包括直径小于1微米的导线和宽度小于1微米的与基底接触并从基底向外延伸的纳米结构以及制备方法。

7. 发明申请

US20090301890A1 FORMATION OF NANOSTRUCTURES COMPRISING COMPOSITIONALLY MODULATED FERROMAGNETIC LAYERS BY PULSED ECD 审中-公开
标题翻译：通过脉冲ECD形成包含组成调节性FERROMAGNETIC层的纳米结构
公开(公告)号：US20090301890A1
公开(公告)日：2009-12-10
申请号：US12540710
申请日：2009-08-13
申请人： Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
发明人： Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
IPC分类号： C25D5/02 , C25D5/18
CPC分类号： C25D5/022 , B82Y25/00 , C25D3/562 , C25D5/10 , C25D5/18 , H01F1/0072 , H01F41/26 , Y10S977/762 , Y10S977/81 , Y10S977/838 , Y10T428/12028 , Y10T428/12465 , Y10T428/12493 , Y10T428/12931 , Y10T428/12944 , Y10T428/12951 , Y10T428/12986 , Y10T428/24967 , Y10T428/2982
摘要： The present invention is related to a method for forming a structure that contains alternating first and second ferromagnetic layers of different material compositions. A substrate containing a supporting matrix with at least one open pore and a conductive base layer is first formed. Electroplating of the substrate is then carried out in an electroplating solution that contains at least one ferromagnetic metal element and one or more additional, different metal elements. A pulsed current with alternating high and low potentials is applied to the conductive base layer of the substrate structure to thereby form alternating ferromagnetic layers of different material compositions in the open pore of the supporting matrix.
摘要翻译：本发明涉及一种用于形成包含不同材料组成的交替的第一和第二铁磁层的结构的方法。首先形成含有具有至少一个开放孔的支撑基体和导电性基底层的基板。然后在含有至少一种铁磁金属元素和一种或多种另外不同的金属元素的电镀溶液中进行基底的电镀。具有交替的高电位和低电位的脉冲电流被施加到衬底结构的导电基底层，从而在支撑矩阵的开孔中形成不同材料组成的交替铁磁层。

8. 发明申请

US20080166584A1 FORMATION OF NANOSTRUCTURES COMPRISING COMPOSITIONALLY MODULATED FERROMAGNETIC LAYERS BY PULSED ECD 有权
标题翻译：通过脉冲ECD形成包含组成调节性FERROMAGNETIC层的纳米结构
公开(公告)号：US20080166584A1
公开(公告)日：2008-07-10
申请号：US11620480
申请日：2007-01-05
申请人： Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
发明人： Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
IPC分类号： H01F1/00 , C25D5/02 , B32B7/02
CPC分类号： C25D5/022 , B82Y25/00 , C25D3/562 , C25D5/10 , C25D5/18 , H01F1/0072 , H01F41/26 , Y10S977/762 , Y10S977/81 , Y10S977/838 , Y10T428/12028 , Y10T428/12465 , Y10T428/12493 , Y10T428/12931 , Y10T428/12944 , Y10T428/12951 , Y10T428/12986 , Y10T428/24967 , Y10T428/2982
摘要： The present invention is related to a method for forming a structure that contains alternating first and second ferromagnetic layers of different material compositions. A substrate containing a supporting matrix with at least one open pore and a conductive base layer is first formed. Electroplating of the substrate is then carried out in an electroplating solution that contains at least one ferromagnetic metal element and one or more additional, different metal elements. A pulsed current with alternating high and low potentials is applied to the conductive base layer of the substrate structure to thereby form alternating ferromagnetic layers of different material compositions in the open pore of the supporting matrix.
摘要翻译：本发明涉及一种用于形成包含不同材料组成的交替的第一和第二铁磁层的结构的方法。首先形成含有具有至少一个开放孔的支撑基体和导电性基底层的基板。然后在含有至少一种铁磁金属元素和一种或多种另外不同的金属元素的电镀溶液中进行基底的电镀。具有交替的高电位和低电位的脉冲电流被施加到衬底结构的导电基底层，从而在支撑矩阵的开孔中形成不同材料组成的交替铁磁层。

9. 发明授权

US09401443B2 Electrodeposition methods of gallium and gallium alloy films and related photovoltaic structures 有权
标题翻译：镓和镓合金膜和相关光伏结构的电沉积方法
公开(公告)号：US09401443B2
公开(公告)日：2016-07-26
申请号：US13604054
申请日：2012-09-05
申请人： Shafaat Ahmed , Hariklia Deligianni , Qiang Huang , Kathleen B. Reuter , Lubomyr T. Romankiw , Raman Vaidyanathan
发明人： Shafaat Ahmed , Hariklia Deligianni , Qiang Huang , Kathleen B. Reuter , Lubomyr T. Romankiw , Raman Vaidyanathan
IPC分类号： C25D3/38 , C25D3/54 , C25D3/56 , C25D3/58 , C25D7/12 , C25D5/10 , H01L31/032 , C25D5/56 , H01L21/02 , H01L31/0749 , H01L23/373
CPC分类号： H01L31/0322 , C25D3/38 , C25D3/54 , C25D3/58 , C25D5/10 , C25D5/56 , C25D7/126 , H01L21/02568 , H01L21/02628 , H01L23/3738 , H01L31/0749 , H01L2224/73253 , Y02E10/541
摘要： Photovoltaic devices and methods for preparing a p-type semiconductor generally include electroplating a layer of gallium or a gallium alloy onto a conductive layer by contacting the conductive layer with a plating bath free of complexing agents including a gallium salt, methane sulfonic acid or sodium sulfate and an organic additive comprising at least one nitrogen atom and/or at least one sulfur atom, and a solvent; adjusting a pH of the solution to be less than 2.6 or greater than 12.6. The photovoltaic device includes an impurity in the p-type semiconductor layer selected from the group consisting of arsenic, antimony, bismuth, and mixtures thereof. Various photovoltaic precursor layers for forming CIS, CGS and CIGS p-type semiconductor structures can be formed by electroplating the gallium or gallium alloys in this manner. Also disclosed are processes for forming a thermal interface of gallium or a gallium alloy.
摘要翻译：用于制备p型半导体的光伏器件和方法通常包括通过使导电层与不含络合剂的镀浴接触将一层镓或镓合金电镀到导电层上，所述络合剂包括镓盐，甲磺酸或硫酸钠和包含至少一个氮原子和/或至少一个硫原子的有机添加剂和溶剂; 调节溶液的pH值小于2.6或大于12.6。光电器件包括选自砷，锑，铋及其混合物的p型半导体层中的杂质。可以通过以这种方式电镀镓或镓合金来形成用于形成CIS，CGS和CIGS p型半导体结构的各种光伏前体层。还公开了形成镓或镓合金的热界面的方法。

10. 发明授权

US08823143B2 Electrodeposition method for forming Ge on semiconductor substrates 有权
标题翻译：用于在半导体衬底上形成Ge的电沉积方法
公开(公告)号：US08823143B2
公开(公告)日：2014-09-02
申请号：US12541499
申请日：2009-08-14
申请人： Stephen W. Bedell , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw , Devendra K. Sadana , Katherine L. Saenger
发明人： Stephen W. Bedell , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/02
CPC分类号： H01L21/823807 , H01L21/0237 , H01L21/02532 , H01L21/02628 , H01L21/02636 , H01L21/02639 , H01L21/28255 , H01L29/1054 , H01L29/78
摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
摘要翻译：提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。

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