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1. 发明申请

US20060118894A1 High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same 有权
公开(公告)号：US20060118894A1
公开(公告)日：2006-06-08
申请号：US11329185
申请日：2006-01-11
申请人： Guy Cohen , Qiqing Ouyang , Jeremy Schaub
发明人： Guy Cohen , Qiqing Ouyang , Jeremy Schaub
IPC分类号： H01L29/82 , H01L27/14 , H01L29/84
CPC分类号： H01L31/1085 , H01L31/02327 , H01L31/035272 , H01L31/105
摘要： A structure (and method for forming the structure) includes a photodetector, a substrate formed under the photodetector, and a barrier layer formed over the substrate. The buried barrier layer preferably includes a single or dual p-n junction, or a bubble layer for blocking or eliminating the slow photon-generated carriers in the region where the drift field is low.

2. 发明授权

US07968915B2 Dual stress memorization technique for CMOS application 有权
标题翻译： CMOS应用的双重应力记忆技术
公开(公告)号：US07968915B2
公开(公告)日：2011-06-28
申请号：US12538110
申请日：2009-08-08
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

3. 发明申请

US20080303101A1 DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION 有权
标题翻译： CMOS应用的双应力记忆技术
公开(公告)号：US20080303101A1
公开(公告)日：2008-12-11
申请号：US11758291
申请日：2007-06-05
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed,
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中，

4. 发明申请

US20080185618A1 STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE Ge-ON-INSULATOR PHOTODETECTOR 有权
标题翻译：高速CMOS兼容Ge-ON-INSULATOR光电转换器的结构和方法
公开(公告)号：US20080185618A1
公开(公告)日：2008-08-07
申请号：US11556755
申请日：2006-11-06
申请人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
发明人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
IPC分类号： H01L27/146
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.
摘要翻译：本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。该器件通过利用掩埋绝缘层来隔离衬底中产生的载流子，通过利用Ge吸收层，在广谱上产生高量子效率，利用薄吸收层和窄电极间隔的低电压操作以及兼容性来实现高带宽通过其平面结构和使用IV族吸收材料的CMOS器件。用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

5. 发明申请

US20080113467A1 STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE Ge-ON-INSULATOR PHOTODETECTOR 有权
公开(公告)号：US20080113467A1
公开(公告)日：2008-05-15
申请号：US11556739
申请日：2006-11-06
申请人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
发明人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
IPC分类号： H01L21/00
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

6. 发明申请

US20080102568A1 SOI BIPOLAR TRANSISTORS WITH REDUCED SELF HEATING 审中-公开
标题翻译：具有减少自加热的SOI双极晶体管
公开(公告)号：US20080102568A1
公开(公告)日：2008-05-01
申请号：US11925983
申请日：2007-10-28
申请人： Qiqing Ouyang , Kai Xiu
发明人： Qiqing Ouyang , Kai Xiu
IPC分类号： H01L21/84 , H01L21/331
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/0623 , H01L27/1203
摘要： A method for constructing a bipolar transistor comprising a collector, a base and an emitter, all located over a substrate, the method including steps of: creating a collector layer over the substrate; etching a path through the collector layer to the substrate; and filling the path with a heat-conductive material.
摘要翻译：一种用于构造双极晶体管的方法，所述双极晶体管包括集电极，基极和发射极，全部位于衬底上，所述方法包括以下步骤：在衬底上方形成集电极层; 蚀刻通过集电极层到基板的路径; 并用导热材料填充路径。

7. 发明授权

US07342294B2 SOI bipolar transistors with reduced self heating 失效
标题翻译：具有自加热降低的SOI双极晶体管
公开(公告)号：US07342294B2
公开(公告)日：2008-03-11
申请号：US11173540
申请日：2005-07-01
申请人： Qiqing Ouyang , Kai Xiu
发明人： Qiqing Ouyang , Kai Xiu
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/0623 , H01L27/1203
摘要： A bipolar transistor includes a collector located over a substrate; and a heat conductive path connecting the substrate to the collector. The heat conductive path is filled with a heat conductive material such as metal or polysilicon. In one embodiment the heat conductive path runs through the collector to extract heat from the collector and drain it to the substrate. In alternate embodiments, the transistor can be a vertical or a lateral device. According to another embodiment, an integrated circuit using BiCMOS technology comprises pnp and npn bipolar transistors with heat conduction from collector to substrate and possibly p-channel and n-channel MOSFETS. According to yet another embodiment, a method for making a transistor in an integrated network comprises steps of etching the heat conducting path through the collector and to the substrate and fill with heat conductive material to provide a heat drain for the transistor comprising the collector.
摘要翻译：双极晶体管包括位于衬底上方的集电极; 以及将基板连接到集电体的导热路径。导热路径填充有诸如金属或多晶硅的导热材料。在一个实施例中，导热路径穿过收集器以从集电器提取热量并将其排出到基板。在替代实施例中，晶体管可以是垂直或横向装置。根据另一实施例，使用BiCMOS技术的集成电路包括具有从集电极到衬底以及可能的p沟道和n沟道MOSFET的热传导的pnp和npn双极晶体管。根据另一个实施例，一种用于在集成网络中制造晶体管的方法包括以下步骤：蚀刻通过集电器和衬底的导热路径，并填充导热材料，以为包括集电器的晶体管提供散热。

8. 发明申请

US20050239241A1 High speed lateral heterojunction MISFETS realized by 2-dimensional bandgap engineering and methods thereof 有权
标题翻译：通过二维带隙工程实现的高速横向异质结MISFETS及其方法
公开(公告)号：US20050239241A1
公开(公告)日：2005-10-27
申请号：US11158726
申请日：2005-06-22
申请人： Qiqing Ouyang , Jack Chu
发明人： Qiqing Ouyang , Jack Chu
IPC分类号： H01L29/78 , H01L21/8238 , H01L29/165 , H01L29/80 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/802 , Y10S438/933
摘要： A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.
摘要翻译：描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变横向沟道结构的方法，其在单晶半导体衬底上结合了漏极，主体和源极区域，其中在晶体管的源极和主体，其中源极区域和沟道独立地相对于身体区域进行晶格应变。本发明通过异质结和晶格应变来减少来自源极区的漏电流的问题，同时通过选择半导体材料和合金组成独立地允许沟道区域中的晶格应变增加迁移率。

9. 发明申请

US20050093021A1 High mobility heterojunction complementary field effect transistors and methods thereof 有权
标题翻译：高迁移率异质结互补场效应晶体管及其方法
公开(公告)号：US20050093021A1
公开(公告)日：2005-05-05
申请号：US10698122
申请日：2003-10-31
申请人： Qiqing Ouyang , Xiangdong Chen
发明人： Qiqing Ouyang , Xiangdong Chen
IPC分类号： H01L27/08 , H01L21/20 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78 , H01L29/786 , H01L29/739
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/7841
摘要： A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body. The SiGe source/drain forms a heterojunction and a metallurgical junction with the Si body that coincide with each other with a tolerance of less than about 10 nm, and preferably less than about 5 nm. The heterostructure source/drain is instrumental in reducing short channel effects. These structures are especially advantageous for PMOS due to increased hole mobility in the compressively strained SiGe channel. Representative embodiments include CMOS structures on bulk and on SOI.
摘要翻译：公开了一种用于高性能场效应器件的结构和制造方法。 MOS结构包括一种导电类型的晶体Si体，在用作空穴的掩埋沟道的Si体上外延生长的应变SiGe层，在用作电子的表面通道的SiGe层上外延生长的Si层，以及源极和漏极，其包含与Si体相反的导电类型的外延沉积的应变SiGe。 SiGe源极/漏极与Si体形成异质结和冶金结，其彼此重合，具有小于约10nm，优选小于约5nm的公差。异质结构源/漏极有助于减少短沟道效应。由于在压缩应变SiGe通道中空穴迁移率增加，这些结构对于PMOS是特别有利的。代表性的实施例包括在本体上和在SOI上的CMOS结构。

10. 发明授权

US08664721B2 FET with FUSI gate and reduced source/drain contact resistance 有权
标题翻译：具有FUSI栅极的FET和降低的源极/漏极接触电阻
公开(公告)号：US08664721B2
公开(公告)日：2014-03-04
申请号：US13569741
申请日：2012-08-08
申请人： Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhen Zhang
IPC分类号： H01L27/12 , H01L29/45
CPC分类号： H01L29/66575 , H01L21/265 , H01L21/28097 , H01L29/458 , H01L29/4908 , H01L29/4975 , H01L29/66507 , H01L29/66545 , H01L29/66772 , H01L29/78 , H01L29/7839
摘要： A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.
摘要翻译：场效应晶体管（FET）包括位于硅层中的源极/漏极硅化物区域; 位于源/漏硅化物区域和硅层之间的源极/漏极界面层; 以及包括位于硅层上的栅极氧化物层，位于栅极氧化物层上的栅极界面层和位于栅极界面层上的栅极硅化物的完全硅化栅极堆叠。

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