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1. 发明授权

US06515912B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06515912B1
公开(公告)日：2003-02-04
申请号：US10018156
申请日：2001-12-10
申请人： Guoqiao Tao , Johannes Dijkstra , Robertus Dominicus Joseph Verhaar , Thomas James Davies
发明人： Guoqiao Tao , Johannes Dijkstra , Robertus Dominicus Joseph Verhaar , Thomas James Davies
IPC分类号： G11C1600
CPC分类号： G11C16/0441
摘要： A semiconductor device comprising a memory cell, which memory cell comprises: a write transistor (TWR) a read transistor (TRE), a sense transistor (TSE) provided with a sense transistor gate, a first sense transistor electrode (7) and a second sense transistor electrode (3), the first sense transistor electrode (7) being connected to a read transistor electrode (9), the sense transistor gate being arranged as a floating gate (FG), said floating gate being separated from the second sense electrode (3) by a sense transistor oxide layer (THINOX) and from a write transistor electrode (1) by a tunnel oxide layer (TUNOX); a voltage source arrangement (5, Vsi_p, Vsi_e) to provide the second sense transistor electrode (3) with a predetermined voltage during programming and erasing, such that no stress induced leakage current occurs in the sense transistor oxide layer (THINOX).
摘要翻译：一种包括存储单元的半导体器件，该存储单元包括：写晶体管（TWR），读晶体管（TRE），具有感测晶体管栅极的检测晶体管（TSE），第一检测晶体管电极（7）感测晶体管电极（3），所述第一感测晶体管电极（7）连接到读取晶体管电极（9），所述感测晶体管栅极被布置为浮置栅极（FG），所述浮置栅极与所述第二感测电极（3）通过感测晶体管氧化物层（THINOX）和由晶体管电极（1）通过隧道氧化物层（TUNOX）;电压源装置（5，Vsi_p，Vsi_e），以提供第二感测晶体管电极）在编程和擦除期间具有预定电压，使得在感测晶体管氧化物层（THINOX）中不产生应力感应泄漏电流。

2. 发明申请

US20110298034A1 MEMORY CELL 审中-公开
标题翻译：记忆体
公开(公告)号：US20110298034A1
公开(公告)日：2011-12-08
申请号：US13152183
申请日：2011-06-02
申请人： Johan Dick Boter , Guoqiao Tao , Guido Jozef Maria Dormans , Joachim Christoph Hans Garbe
发明人： Johan Dick Boter , Guoqiao Tao , Guido Jozef Maria Dormans , Joachim Christoph Hans Garbe
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , G11C16/3418 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory cell (200) comprising a floating gate transistor (206) comprising a floating gate (10) positioned between a control gate (14) and a first channel region (232) and an access gate transistor (208) comprising an access gate (22) and a second channel region (234), the first channel region (232) comprising a first implant (242) with a first dosage level (234), and the second channel region comprising a second implant (244) having a second dosage level, the first dosage level being less than the second dosage level.
摘要翻译：一种包括浮置晶体管（206）的非易失性存储单元（200），其包括位于控制栅极（14）和第一沟道区域（232）之间的浮动栅极（10）和存取栅极晶体管（208）存取栅极（22）和第二沟道区域（234），所述第一沟道区域（232）包括具有第一剂量级别（234）的第一植入物（242），所述第二沟道区域包括第二植入物（244）第二剂量水平，第一剂量水平小于第二剂量水平。

3. 发明申请

US20050094439A1 Non-voltile memory test structure and method 有权
标题翻译：非电压记忆测试结构和方法
公开(公告)号：US20050094439A1
公开(公告)日：2005-05-05
申请号：US10505835
申请日：2003-01-31
申请人： Guoqiao Tao
发明人： Guoqiao Tao
IPC分类号： G11C16/02 , G11C16/04 , G11C29/04 , G11C29/06 , G11C29/12 , G11C11/34
CPC分类号： G11C29/12
摘要： The invention relates to a non-volatile memory test structure, comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising at least a memory transistor and having a source terminal, a gate terminal and a drain terminal. In order to provide a fast and effective test structure to be used for fast reliability evaluation in monitoring of non-volatile memory elements on every wafer it is proposed according to the present invention that:—a group of said memory cells is connected in parallel,—the source terminals of the memory cells in the group are connected together and to a source line,—the drain terminals of the memory cells in the group are connected together and to a drain line,—the gate terminals of the memory cells in the group are connected together and to a gate line, and—said gate line has two connections to apply an electrical current to said gate line for using it as a heating means.
摘要翻译：本发明涉及一种非易失性存储器测试结构，包括以行和列排列的多个存储单元，每个存储单元至少包括存储晶体管，并具有源极端子，栅极端子和漏极端子。为了提供快速有效的测试结构，用于在每个晶片上的非易失性存储器元件的监视中的快速可靠性评估，根据本发明提出： - 一组所述存储单元并联连接， - 组中的存储器单元的源极端子连接到源极线， - 组中的存储器单元的漏极端子连接到漏极线， - 存储器单元的栅极端子组连接在一起并连接到栅极线，并且所述栅极线具有两个连接，以将电流施加到所述栅极线以将其用作加热装置。

4. 发明授权

US09165663B2 Secure non-volatile memory device and method of protecting data therein 有权
标题翻译：安全的非易失性存储器件及其中的数据保护方法
公开(公告)号：US09165663B2
公开(公告)日：2015-10-20
申请号：US12443511
申请日：2007-09-27
申请人： Guoqiao Tao
发明人： Guoqiao Tao
IPC分类号： G06F12/14 , G11C16/22 , G06F21/72 , G06F21/79 , G11C11/00
CPC分类号： G11C16/22 , G06F12/1408 , G06F21/72 , G06F21/79 , G11C11/005
摘要： The invention relates to a non-volatile memory device comprising: an input for providing external data to be stored on the non-volatile memory device; a first non-volatile memory block and a second non-volatile memory block, the first non-volatile memory block and the second non-volatile memory block being provided on a single die, wherein the first non-volatile memory block and second non-volatile memory block are of a different type such that the first non-volatile memory block and the second non-volatile memory block require incompatible external attack techniques in order to retrieve data there from; and—an encryption circuit for encrypting the external data forming encrypted data using unique data from at least the first non-volatile memory block as an encryption key, the encrypted data at least being stored into the second non-volatile memory block. The invention further relates to method of protecting data in a non-volatile memory device.
摘要翻译：本发明涉及一种非易失性存储器件，包括：用于提供要存储在非易失性存储器件上的外部数据的输入; 第一非易失性存储器块和第二非易失性存储器块，第一非易失性存储器块和第二非易失性存储器块被提供在单个管芯上，其中第一非易失性存储器块和第二非易失性存储器块，易失性存储器块是不同类型的，使得第一非易失性存储器块和第二非易失性存储器块需要不兼容的外部攻击技术以从其中检索数据; 以及加密电路，用于使用来自至少所述第一非易失性存储器块的唯一数据作为加密密钥来加密形成加密数据的外部数据，所述加密数据至少存储在所述第二非易失性存储器块中。本发明还涉及在非易失性存储器件中保护数据的方法。

5. 发明授权

US08169811B2 Non-volatile re-programmable memory device 有权
标题翻译：非易失性可重新编程存储器件
公开(公告)号：US08169811B2
公开(公告)日：2012-05-01
申请号：US12835588
申请日：2010-07-13
申请人： Yuan Li , Guoqiao Tao
发明人： Yuan Li , Guoqiao Tao
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C7/04 , G11C7/24 , G11C13/0007 , G11C13/0059 , H01L45/08 , H01L45/1226 , H01L45/14
摘要： A memory device including a non-volatile re-programmable memory cell is provided. In connection with various example embodiments, the memory cell is a single resistor located between a first and second node. The resistor stores different resistance states corresponding to different resistance values set by SiCr-facilitated migration. The SiCr-facilitated migration occurs in response to energy presented between the first and second nodes. The application of a signal to a first node of the memory cell resistor forces the migration of elements along the memory cell resistor to set the resistance value of the memory cell resistor. The application of a second signal of approximately equal strength to the second node reverses the change and resistance and returns the memory cell to the previous resistance level. In some implementations the resistor is made of SiCr.
摘要翻译：提供了包括非易失性可再编程存储单元的存储器件。结合各种示例实施例，存储器单元是位于第一和第二节点之间的单个电阻器。电阻器存储对应于由SiCr促进迁移设置的不同电阻值的不同电阻状态。 SiCr促进的迁移响应于第一和第二节点之间的能量而发生。将信号施加到存储单元电阻器的第一节点迫使元件沿着存储单元电阻器的迁移以设置存储单元电阻器的电阻值。对第二节点施加大致相等强度的第二信号反转该变化和电阻，并将存储器单元返回到先前的电阻电平。在一些实施方案中，电阻器由SiCr制成。

6. 发明申请

US20120043600A1 Floating-Gate Device and Method Therefor 审中-公开
标题翻译：浮门装置及其方法
公开(公告)号：US20120043600A1
公开(公告)日：2012-02-23
申请号：US12858977
申请日：2010-08-18
申请人： Henderikus Albert Van der Vegt , Guido Jozef Maria Dormans , Johan Dick Boter , Guoqiao Tao
发明人： Henderikus Albert Van der Vegt , Guido Jozef Maria Dormans , Johan Dick Boter , Guoqiao Tao
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/40114 , G11C16/0416 , H01L27/11517 , H01L29/42324 , H01L29/4916
摘要： Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.
摘要翻译：非易失性浮动栅极器件和方法涉及相对于热处理设置或维持阈值电压特性。关于各种实施例，浮动栅极器件包括其中具有杂质的多晶硅材料。杂质与多晶材料相互作用以抵抗热处理期间多晶硅材料的晶粒尺寸变化，并且相对于浮动栅极器件的阈值电压设定电荷存储特性。

7. 发明授权

US07907447B2 Secure non-volatile memory device and method of protecting data therein 有权
标题翻译：安全的非易失性存储器件及其中的数据保护方法
公开(公告)号：US07907447B2
公开(公告)日：2011-03-15
申请号：US12443528
申请日：2007-09-27
申请人： Guoqiao Tao , Steven V. E. S. Van Dijk
发明人： Guoqiao Tao , Steven V. E. S. Van Dijk
IPC分类号： G11C11/34
CPC分类号： G11C16/22
摘要： The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1′, D1″) into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.
摘要翻译：本发明涉及一种非易失性存储器件，包括：用于提供要存储在非易失性存储器件上的外部数据（D1）的输入; 和第一非易失性存储器块（100）和第二非易失性存储器块（200），所述第一非易失性存储器块（100）和所述第二非易失性存储器块（200）设置在单个管芯（10），其中第一非易失性存储器块（100）和第二非易失性存储器块（200）是不同类型的，使得第一非易失性存储器块（100）和第二非易失性存储器块（200）需要不兼容的外部攻击技术以便从其中检索数据，外部数据（D1）以分布式方式（D1'，D1“）存储到第一非易失性存储器块（100）和第二非易失性存储器块非易失性存储器块（200）。本发明还涉及在非易失性存储设备中保护数据的方法。

8. 发明申请

US20120014160A1 Non-Volatile Re-Programmable Memory Device 有权
标题翻译：非易失性可重新编程的存储器件
公开(公告)号：US20120014160A1
公开(公告)日：2012-01-19
申请号：US12835588
申请日：2010-07-13
申请人： Yuan Li , Guoqiao Tao
发明人： Yuan Li , Guoqiao Tao
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C7/04 , G11C7/24 , G11C13/0007 , G11C13/0059 , H01L45/08 , H01L45/1226 , H01L45/14
摘要： A memory device including a non-volatile re-programmable memory cell is provided. In connection with various example embodiments, the memory cell is a single resistor located between a first and second node. The resistor stores different resistance states corresponding to different resistance values set by SiCr-facilitated migration. The SiCr-facilitated migration occurs in response to energy presented between the first and second nodes. The application of a signal to a first node of the memory cell resistor forces the migration of elements along the memory cell resistor to set the resistance value of the memory cell resistor. The application of a second signal of approximately equal strength to the second node reverses the change and resistance and returns the memory cell to the previous resistance level. In some implementations the resistor is made of SiCr.
摘要翻译：提供了包括非易失性可再编程存储单元的存储器件。结合各种示例实施例，存储器单元是位于第一和第二节点之间的单个电阻器。电阻器存储对应于由SiCr促进迁移设置的不同电阻值的不同电阻状态。 SiCr促进的迁移响应于第一和第二节点之间的能量而发生。将信号施加到存储单元电阻器的第一节点迫使元件沿着存储单元电阻器的迁移以设置存储单元电阻器的电阻值。对第二节点施加大致相等强度的第二信号反转该变化和电阻，并将存储器单元返回到先前的电阻电平。在一些实施方案中，电阻器由SiCr制成。

9. 发明申请

US20100002511A1 SECURE NON-VOLATILE MEMORY DEVICE AND METHOD OF PROTECTING DATA THEREIN 有权
标题翻译：安全的非易失性存储器件及其保护数据的方法
公开(公告)号：US20100002511A1
公开(公告)日：2010-01-07
申请号：US12443528
申请日：2007-09-27
申请人： Guoqiao Tao , Steven V. E. S. Van Dijk
发明人： Guoqiao Tao , Steven V. E. S. Van Dijk
IPC分类号： G11C16/22 , G11C16/02
CPC分类号： G11C16/22
摘要： The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1′, D1″) into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.
摘要翻译：本发明涉及一种非易失性存储器件，包括：用于提供要存储在非易失性存储器件上的外部数据（D1）的输入; 和第一非易失性存储器块（100）和第二非易失性存储器块（200），所述第一非易失性存储器块（100）和所述第二非易失性存储器块（200）设置在单个管芯（10），其中第一非易失性存储器块（100）和第二非易失性存储器块（200）是不同类型的，使得第一非易失性存储器块（100）和第二非易失性存储器块（200）需要不兼容的外部攻击技术以便从其中检索数据，外部数据（D1）以分布式方式（D1'，D1“）存储到第一非易失性存储器块（100）和第二非易失性存储器块（200）。本发明还涉及在非易失性存储器件中保护数据的方法。

10. 发明授权

US06921946B2 Test structure for electrical well-to-well overlay 失效
标题翻译：电气井对覆盖层的测试结构
公开(公告)号：US06921946B2
公开(公告)日：2005-07-26
申请号：US10320266
申请日：2002-12-16
申请人： Guoqiao Tao , Roy Arthur Colclaser
发明人： Guoqiao Tao , Roy Arthur Colclaser
IPC分类号： H01L23/544 , H01L29/00
CPC分类号： H01L22/34
摘要： There is a test structure on a semiconductor substrate for testing misalignment between adjacent implanted regions of opposite conductivity in a semiconductor device. In an example embodiment, the test structure includes a first and a second triple well structure; the second triple well structure is adjacent to the first triple well-structure in a first direction. Each structure includes a lower buried n-well region, a p-well region, a p+-region, an n-well region and a base n+-region, wherein a central base portion and a central n-well region portion are common to the first and the second structure, with the central base portion as a symmetry line with a width. Between the central base portion and the p-well region in the first triple well-structure a first overlay, and between the central base portion and the p-well region in the second triple well-structure a second overlay is provided.
摘要翻译：在半导体衬底中存在用于测试半导体器件中具有相反导电性的相邻注入区之间的未对准的测试结构。在示例性实施例中，测试结构包括第一和第二三重阱结构; 第二三阱结构在第一方向上与第一三重阱结构相邻。每个结构包括下掩埋的n阱区，p阱区，p + +区，n阱区和碱n + +区，其中第一和第二结构共同的中心基部和中心n阱区，其中心基部为具有宽度的对称线。在第一三重阱结构中的中心基部和p阱区之间的第一覆盖层，以及在第二三阱结构中的中心基部和p阱区之间提供第二覆盖层。

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