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1. 发明申请

US20110298034A1 MEMORY CELL 审中-公开
标题翻译：记忆体
公开(公告)号：US20110298034A1
公开(公告)日：2011-12-08
申请号：US13152183
申请日：2011-06-02
申请人： Johan Dick Boter , Guoqiao Tao , Guido Jozef Maria Dormans , Joachim Christoph Hans Garbe
发明人： Johan Dick Boter , Guoqiao Tao , Guido Jozef Maria Dormans , Joachim Christoph Hans Garbe
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , G11C16/3418 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory cell (200) comprising a floating gate transistor (206) comprising a floating gate (10) positioned between a control gate (14) and a first channel region (232) and an access gate transistor (208) comprising an access gate (22) and a second channel region (234), the first channel region (232) comprising a first implant (242) with a first dosage level (234), and the second channel region comprising a second implant (244) having a second dosage level, the first dosage level being less than the second dosage level.
摘要翻译：一种包括浮置晶体管（206）的非易失性存储单元（200），其包括位于控制栅极（14）和第一沟道区域（232）之间的浮动栅极（10）和存取栅极晶体管（208）存取栅极（22）和第二沟道区域（234），所述第一沟道区域（232）包括具有第一剂量级别（234）的第一植入物（242），所述第二沟道区域包括第二植入物（244）第二剂量水平，第一剂量水平小于第二剂量水平。

2. 发明申请

US20120043600A1 Floating-Gate Device and Method Therefor 审中-公开
标题翻译：浮门装置及其方法
公开(公告)号：US20120043600A1
公开(公告)日：2012-02-23
申请号：US12858977
申请日：2010-08-18
申请人： Henderikus Albert Van der Vegt , Guido Jozef Maria Dormans , Johan Dick Boter , Guoqiao Tao
发明人： Henderikus Albert Van der Vegt , Guido Jozef Maria Dormans , Johan Dick Boter , Guoqiao Tao
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/40114 , G11C16/0416 , H01L27/11517 , H01L29/42324 , H01L29/4916
摘要： Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.
摘要翻译：非易失性浮动栅极器件和方法涉及相对于热处理设置或维持阈值电压特性。关于各种实施例，浮动栅极器件包括其中具有杂质的多晶硅材料。杂质与多晶材料相互作用以抵抗热处理期间多晶硅材料的晶粒尺寸变化，并且相对于浮动栅极器件的阈值电压设定电荷存储特性。

3. 发明授权

US07006381B2 Semiconductor device having a byte-erasable EEPROM memory 有权
标题翻译：具有字节可擦除EEPROM存储器的半导体器件
公开(公告)号：US07006381B2
公开(公告)日：2006-02-28
申请号：US10497262
申请日：2002-10-24
申请人： Guido Jozef Maria Dormans , Robertus Dominicus Joseph Verhaar , Joachim Christoph Hans Garbe
发明人： Guido Jozef Maria Dormans , Robertus Dominicus Joseph Verhaar , Joachim Christoph Hans Garbe
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/16
摘要： The invention relates to a semiconductor device having a byte-erasable EEPROM memory comprising a matrix of rows and columns of memory cells. In order to provide a semiconductor device having a byte-erasable EEPROM which has a reduced chip size and increased density and which is suitable for low-power applications it is proposed according to the present invention that the memory cells each comprise a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, the selection transistor being further connected to a source line of the byte-erasable EEPROM memory, which source line is common for a plurality of memory cells, and the memory transistor being further connected to a bit line of the byte-erasable EEPROM memory, wherein the columns of memory cells are located in separate p-type wells separated by n-type wells. Preferably, high voltage switching elements are provided for dividing global control gates into local control gates for each column of bytes.
摘要翻译：本发明涉及一种具有字节可擦除EEPROM存储器的半导体器件，其包括存储器单元的行和列的矩阵。为了提供具有字节可擦除EEPROM的半导体器件，其具有减小的芯片尺寸和增加的密度，并且适用于低功率应用，根据本发明提出，存储器单元各自包括选择晶体管，其具有选择栅极，与串联布置的具有浮置栅极和控制栅极的存储晶体管，所述选择晶体管进一步连接到所述字节可擦除EEPROM存储器的源极线，所述源极线对于多个存储单元是公共的并且存储晶体管进一步连接到字节可擦除EEPROM存储器的位线，其中存储器单元的列位于由n型阱分离的单独的p型阱中。优选地，提供高压开关元件，用于将全局控制门分成用于每列字节的本地控制门。

4. 发明授权

US08278202B2 Conductive spacers extended floating gates 有权
标题翻译：导电间隔物延伸浮动门
公开(公告)号：US08278202B2
公开(公告)日：2012-10-02
申请号：US12176868
申请日：2008-07-21
申请人： Antonius Maria Petrus Johannes Hendricks , Josephus Franciscus Antonius Maria Guelen , Guido Jozef Maria Dormans
发明人： Antonius Maria Petrus Johannes Hendricks , Josephus Franciscus Antonius Maria Guelen , Guido Jozef Maria Dormans
IPC分类号： H01L21/00
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and then forming the control gate over the floating gate and the spacers.
摘要翻译：一种在具有浮动栅极和控制栅极的半导体器件的基板上制造方法。该方法包括以下步骤：首先在衬底中形成隔离区，然后在衬底上形成浮置栅极。该方法还包括使用间隔物延伸浮动栅极，然后在浮动栅极和间隔物上形成控制栅极。

5. 发明申请

US20090087976A1 Conductive Spacers Extended Floating Gates 有权
标题翻译：导电隔板扩展浮动门
公开(公告)号：US20090087976A1
公开(公告)日：2009-04-02
申请号：US12176868
申请日：2008-07-21
申请人： Antonius Maria Petrus Hendriks , Josephus Franciscus Antoniu Guelen , Guido Jozef Maria Dormans
发明人： Antonius Maria Petrus Hendriks , Josephus Franciscus Antoniu Guelen , Guido Jozef Maria Dormans
IPC分类号： H01L21/3205
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and then forming the control gate over the floating gate and the spacers.
摘要翻译：一种在具有浮动栅极和控制栅极的半导体器件的基板上制造方法。该方法包括以下步骤：首先在衬底中形成隔离区，然后在衬底上形成浮置栅极。该方法还包括使用间隔物延伸浮动栅极，然后在浮动栅极和间隔物上形成控制栅极。

6. 发明授权

US08063429B2 Conductive spacers extended floating gates 有权
标题翻译：导电间隔物延伸浮动门
公开(公告)号：US08063429B2
公开(公告)日：2011-11-22
申请号：US12173440
申请日：2008-07-15
申请人： Antonius Maria Petrus Johannes Hendriks , Josephus Franciscus Antonius Maria Guelen , Guido Jozef Maria Dormans
发明人： Antonius Maria Petrus Johannes Hendriks , Josephus Franciscus Antonius Maria Guelen , Guido Jozef Maria Dormans
IPC分类号： H01L21/00
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A method for manufacturing on a substrate a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone in the substrate, thereafter forming the floating gate on the substrate, thereafter extending the floating gate using polysilicon spacers, and thereafter forming the control gate over the floating gate and the polysilicon spacers. Such a semiconductor device may be used in flash memory cells or EEPROMs.
摘要翻译：描述了在衬底上制造具有改善的浮栅到控制栅耦合比的半导体器件的方法。该方法包括以下步骤：首先在衬底中形成隔离区，之后在衬底上形成浮置栅极，然后使用多晶硅间隔物延伸浮置栅极，然后在浮置栅极和多晶硅间隔物上形成控制栅极。这样的半导体器件可以用在闪存单元或EEPROM中。

7. 发明授权

US07416939B2 Conductive spacers extended floating gates 有权
标题翻译：导电间隔物延伸浮动门
公开(公告)号：US07416939B2
公开(公告)日：2008-08-26
申请号：US10518736
申请日：2003-06-12
申请人： Antonius Maria Petrus Johannes Hendriks , Josephus Franciscus Antonius Maria Guelen , Guido Jozef Maria Dormans
发明人： Antonius Maria Petrus Johannes Hendriks , Josephus Franciscus Antonius Maria Guelen , Guido Jozef Maria Dormans
IPC分类号： H01L21/00
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A method for manufacturing on a substrate (24) a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone (22) in the substrate (24), thereafter forming the floating gate (28) on the substrate (24), thereafter extending the floating gate (28) using polysilicon spacers (40), and thereafter forming the control gate (44) over the floating gate (28) and the polysilicon spacers (40). Such a semiconductor device may be used in flash memory cells or EEPROMs.
摘要翻译：描述了一种用于在衬底（24）上制造具有改善的浮栅到控制栅耦合比的半导体器件的方法。该方法包括以下步骤：首先在衬底（24）中形成隔离区（22），然后在衬底（24）上形成浮动栅极（28），然后使用多晶硅间隔物（40）延伸浮置栅极（28），然后在浮动栅极（28）和多晶硅间隔物（40）上形成控制栅极（44）。这样的半导体器件可以用在闪存单元或EEPROM中。

8. 发明授权

US07148103B2 Multilevel poly-Si tiling for semiconductor circuit manufacture 有权
标题翻译：用于半导体电路制造的多层多晶硅拼接
公开(公告)号：US07148103B2
公开(公告)日：2006-12-12
申请号：US10492888
申请日：2002-10-16
申请人： Antonius Maria Petrus Johannes Hendriks , Guido Jozef Maria Dormans , Robertus Dominicus Joseph Verhaar
发明人： Antonius Maria Petrus Johannes Hendriks , Guido Jozef Maria Dormans , Robertus Dominicus Joseph Verhaar
IPC分类号： H01L21/8242
CPC分类号： H01L27/11526 , H01L21/32137 , H01L21/8234 , H01L27/11531
摘要： Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE); manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE; providing a tile structure (25; 26); providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); and exposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.
摘要翻译：一种制造半导体器件的方法，包括第一基线技术电子电路（1）和第二选择技术电子电路（2）作为片上系统的功能部件，通过以下步骤：制造第一电子电路（1）通过使其暴露的层部分经受反应离子蚀刻（RIE）而被图案化的第一导电层（6; 6）; 用第二导电层（6; 8）制造所述第二电子电路（2），所述第二导电层通过使其暴露的层部分经受RIE而被图案化; 提供瓷砖结构（25; 26）; 在与第二导电层（6; 8）相同的处理步骤中制造的至少一个虚设导电层（6; 8）提供瓦片结构（25; 26）; 并且至少部分地暴露所述虚设导电层（6; 8），以获得暴露的虚设层部分，以及当所述第二（6; 8）导电层经受RIE时也暴露部分的RIE蚀刻。

9. 发明授权

US06815755B2 Non-volatile memory cells, high voltage transistors and logic transistors integrated on a single chip 有权
标题翻译：集成在单个芯片上的非易失性存储单元，高压晶体管和逻辑晶体管
公开(公告)号：US06815755B2
公开(公告)日：2004-11-09
申请号：US10390946
申请日：2003-03-18
申请人： Roy Arthur Colclaser , Guido Jozef Maria Dormans , Donald Robert Wolters
发明人： Roy Arthur Colclaser , Guido Jozef Maria Dormans , Donald Robert Wolters
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25); the at least one memory cell having a floating gate (5), a tunnel oxide layer (11) between the floating gate and the substrate (1), a control gate (15), and a control oxide layer (13) between the control gate (15) and the floating gate (5); the at least one logic transistor (25) having a logic transistor gate (5′, 15″) and a logic transistor gate oxide (11″) between the logic transistor gate (5′, 15″) and the substrate (1), the tunnel oxide layer (11) of the memory cell (3) and the logic transistor gate oxide (11″) having a same or substantially same predetermined first thickness. The invention also relates to a method of manufacturing such a device and to such a device that also comprises a high voltage transistor (17) which is optionally made so as to be an integral part of at least the memory cell (3).
摘要翻译：具有在单个衬底（1）上的至少一个存储器单元（3）和至少一个逻辑晶体管（25）的半导体器件;所述至少一个存储器单元具有浮置栅极（5），隧道氧化物层（11）所述浮栅和所述衬底（1），所述控制栅极（15）和所述控制栅极（15）和所述浮动栅极（5）之间的控制氧化物层（13）;所述至少一个逻辑晶体管（25）具有在逻辑晶体管栅极（5'，15“）和衬底（1）之间的逻辑晶体管栅极（5'，15”）和逻辑晶体管栅极氧化物（11“），隧道氧化物层（11）的存储单元（3）和逻辑晶体管栅极氧化物（11“）具有相同或基本相同的预定第一厚度。本发明还涉及一种制造这种器件的方法以及这种器件，其还包括高压晶体管（17），其可选地制成为至少是存储器单元（3）的整体部分。

10. 发明授权

US06518619B2 Virtual-ground, split-gate flash memory cell arrangements and method for producing same 有权
标题翻译：虚拟地，分闸闪存单元布置及其制造方法
公开(公告)号：US06518619B2
公开(公告)日：2003-02-11
申请号：US09741667
申请日：2000-12-19
申请人： Robertus Dominicus Joseph Verhaar , Guido Jozef Maria Dormans
发明人： Robertus Dominicus Joseph Verhaar , Guido Jozef Maria Dormans
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0425 , H01L21/28273 , H01L27/11519 , H01L29/42328 , H01L29/66825 , Y10S257/90
摘要： A memory cell including: (a) a semiconductor substrate (1) provided with first and second diffusion layers (8); (b) a floating gate (11) on a floating gate insulating film (9); (c) a selection gate (4) on a selection gate insulating film (2); (d) a control gate (13) on a control gate insulating film (12); (e) the first and second diffusion layers (8) being arranged as the source and the drain of a field effect transistor structure, and the floating gate (11), selection gate (4) and control gate (13) being arranged as series field effect gates in the field effect transistor structure.
摘要翻译：一种存储单元，包括：（a）设置有第一和第二扩散层（8）的半导体衬底（1）;（b）浮置栅极绝缘膜（9）上的浮动栅极（11）;（c）选择栅极（4）在选择栅极绝缘膜（2）上;（d）控制栅绝缘膜（12）上的控制栅极（13）;（e）第一和第二扩散层（8）被布置为源极，场效应晶体管结构的漏极，以及浮置栅极（11），选择栅极（4）和控制栅极（13）被布置为场效应晶体管结构中的串联场效应栅极。

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