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1. 发明授权

US5913199A Process and system for automatic, computer-system-supported optimisation 失效
标题翻译：自动，计算机系统支持优化的过程和系统
公开(公告)号：US5913199A
公开(公告)日：1999-06-15
申请号：US765478
申请日：1996-12-20
申请人： Gunter Dueck , Jochen Eddelbuttel , Martin Gerhardt , Christof Pospiech , Hans-Georg Reusch , Tobias Scheuer , Klaus Volk , Hans-Martin Wallmeier
发明人： Gunter Dueck , Jochen Eddelbuttel , Martin Gerhardt , Christof Pospiech , Hans-Georg Reusch , Tobias Scheuer , Klaus Volk , Hans-Martin Wallmeier
IPC分类号： G01C21/34 , G06Q10/00 , G06F17/60
CPC分类号： G06Q10/047 , G06Q10/063 , G06Q10/06316
摘要： In a process and a system for automatic, computer-system-supported optimization and the search for a state x dependent on at least one parameter P, for which f(x) as a measure of the quality of x assumes an extremum, an initial solution, i.e. a state x, is found as an initial state and a further state y different from x is found by means of an elementary change in an individual parameter P from x. If the result of a comparison of the target function values f(x) and f(y) is that f(y) is poorer than f(x) by more than a threshold value T, y is rejected, x is retained and a fresh adjacent state of x is found. If f(y) is at least as great as f(x)-T, there is a transition to state y. The threshold T is successively reduced to zero.
摘要翻译： PCT No.PCT / EP95 / 01961 Sec。 371日期1996年12月20日第 102（e）日期1996年12月20日PCT提交1995年5月23日PCT公布。出版物WO96 / 02040 日期1996年1月25日在自动，计算机系统支持的优化和根据至少一个参数P的状态x的搜索的过程和系统中，其中f（x）作为x的质量的度量发现极值，即初始解，即状态x，作为初始状态，并且通过来自x的单个参数P的基本变化，找到与x不同的另外状态y。如果目标函数值f（x）和f（y）的比较的结果是f（y）比f（x）更差超过阈值T，则y被拒绝，x被保留找到新的相邻状态的x。如果f（y）至少与f（x）-T一样大，则转移到状态y。阈值T依次减小到零。

2. 发明授权

US07494906B2 Technique for transferring strain into a semiconductor region 有权
标题翻译：将应变转移到半导体区域的技术
公开(公告)号：US07494906B2
公开(公告)日：2009-02-24
申请号：US11112498
申请日：2005-04-22
申请人： Thorsten Kammler , Martin Gerhardt , Frank Wirbeleit
发明人： Thorsten Kammler , Martin Gerhardt , Frank Wirbeleit
IPC分类号： H01L21/8238 , H01L21/425
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/7624 , H01L21/84 , H01L29/0649 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/7843 , Y10S438/938
摘要： A dislocation region is formed by implanting a light inert species, such as hydrogen, to a specified depth and with a high concentration, and by heat treating the inert species to create “nano” bubbles, which enable a certain mechanical decoupling to underlying device regions, thereby allowing a more efficient creation of strain that is induced by an external stress-generating source. In this way, strain may be created in a channel region of a field effect transistor by, for instance, a stress layer or sidewall spacers formed in the vicinity of the channel region.
摘要翻译：通过将诸如氢的轻惰性物质注入指定的深度和高浓度，并且通过热处理惰性物质以产生“纳米”气泡来形成位错区域，这使得能够对下面的器件区域进行一定的机械解耦从而允许更有效地产生由外部应力产生源引起的应变。以这种方式，可以通过例如形成在沟道区附近的应力层或侧壁间隔在场效应晶体管的沟道区域中产生应变。

3. 发明授权

US07462524B1 Methods for fabricating a stressed MOS device 有权
标题翻译：制造应力MOS器件的方法
公开(公告)号：US07462524B1
公开(公告)日：2008-12-09
申请号：US11205797
申请日：2005-08-16
申请人： Igor Peidous , Martin Gerhardt , David E. Brown
发明人： Igor Peidous , Martin Gerhardt , David E. Brown
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/165 , H01L29/66636 , H01L29/7845 , H01L29/7848
摘要： Methods are provided for fabricating a stressed MOS device. One method comprises the steps of providing a substrate of a monocrystalline semiconductor material having a first lattice constant, and forming a conductive gate electrode overlying the substrate, the gate electrode having opposing sides and having a thickness. Sidewall spacers are formed on the opposing sides of the gate electrode and trenches are etched in the semiconductor substrate in alignment with the sidewall spacers. A portion of the thickness of the conductive gate electrode is also etched to leave a remaining portion of the conductive gate electrode. A stress inducing layer of material is grown on the remaining portion of the conductive gate electrode and filling the trenches, the stress inducing layer of material having a second lattice constant different than the first lattice constant.
摘要翻译：提供了制造应力MOS器件的方法。一种方法包括以下步骤：提供具有第一晶格常数的单晶半导体材料的衬底，以及形成覆盖衬底的导电栅电极，栅电极具有相对的侧面并具有厚度。侧壁间隔物形成在栅电极的相对侧上，并且沟槽在半导体衬底中被蚀刻以与侧壁间隔物对齐。还蚀刻导电栅电极的厚度的一部分以留下导电栅电极的剩余部分。在导电栅电极的剩余部分上生长材料的应力诱导层，并填充沟槽，具有不同于第一晶格常数的第二晶格常数的材料的应力诱导层。

4. 发明申请

US20080026552A1 METHOD OF ENHANCING LITHOGRAPHY CAPABILITIES DURING GATE FORMATION IN SEMICONDUCTORS HAVING A PRONOUNCED SURFACE TOPOGRAPHY 有权
标题翻译：在具有预定表面形貌的半导体中增加栅格形成过程中的刻蚀能力的方法
公开(公告)号：US20080026552A1
公开(公告)日：2008-01-31
申请号：US11773631
申请日：2007-07-05
申请人： Martin Gerhardt , Martin Trentzsch , Markus Forsberg , Manfred Horstmann
发明人： Martin Gerhardt , Martin Trentzsch , Markus Forsberg , Manfred Horstmann
IPC分类号： H01L21/4763
CPC分类号： H01L21/28123 , H01L29/66772
摘要： In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.
摘要翻译：在用于在半导体岛上形成晶体管的台面隔离结构中，执行附加的平面化步骤以增强栅极图案化工艺的均匀性。在一些说明性实施例中，当栅电极材料形成在未填充的隔离沟槽上方时，栅电极材料可以例如基于CMP平坦化，以补偿高度不均匀的表面形貌。因此，由于关键栅极图案化工艺的增强，台面隔离策略的显着优点可能与高度的可扩展性相结合。

5. 发明授权

US08541885B2 Technique for enhancing transistor performance by transistor specific contact design 有权
标题翻译：通过晶体管特定接触设计增强晶体管性能的技术
公开(公告)号：US08541885B2
公开(公告)日：2013-09-24
申请号：US13107515
申请日：2011-05-13
申请人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
发明人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823871 , H01L23/485 , H01L29/41758 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
摘要翻译：通过局部地适应接触结构的尺寸和/或密度，例如，在单个晶体管内或以更全球化的方式，可以增加先进半导体器件的整体性能。因此，可以考虑接触结构和局部器件特性之间的相互作用。另一方面，可以保持与常规工艺策略的高度兼容性。

6. 发明授权

US07994059B2 Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device 有权
标题翻译：通过在半导体器件中的双应力衬垫上方使用附加应力层来增强层间电介质中的应力转移
公开(公告)号：US07994059B2
公开(公告)日：2011-08-09
申请号：US11865796
申请日：2007-10-02
申请人： Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
发明人： Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
IPC分类号： H01L21/331
CPC分类号： H01L29/7833 , H01L21/76802 , H01L21/76825 , H01L21/76832 , H01L21/76837 , H01L21/823412 , H01L21/823807 , H01L27/092 , H01L29/7843
摘要： By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.
摘要翻译：通过在对具有不同的本征应力的介电衬垫进行图案化之后形成附加的应力介电材料，可以获得在晶体管中性能的显着提高，同时在高比例尺度的半导体器件中形成各个接触开口期间基本上不会构图不均匀性。附加介电层可以被提供任何类型的固有应力，而不管先前选择的图案化序列如何。

7. 发明授权

US07964458B2 Method for forming a strained transistor by stress memorization based on a stressed implantation mask 有权
标题翻译：基于应力注入掩模的应力记忆形成应变晶体管的方法
公开(公告)号：US07964458B2
公开(公告)日：2011-06-21
申请号：US11746106
申请日：2007-05-09
申请人： Frank Wirbeleit , Roman Boschke , Martin Gerhardt
发明人： Frank Wirbeleit , Roman Boschke , Martin Gerhardt
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L21/7624 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.
摘要翻译：通过使用具有高固有应力的注入掩模，可以提供SMT序列，其中可以避免额外的光刻步骤。因此，可以提供应变源而不显着地有助于整个工艺的复杂性。

8. 发明授权

US07659170B2 Method of increasing transistor drive current by recessing an isolation trench 有权
标题翻译：通过凹陷隔离沟槽来增加晶体管驱动电流的方法
公开(公告)号：US07659170B2
公开(公告)日：2010-02-09
申请号：US11620406
申请日：2007-01-05
申请人： Christoph Schwan , Manfred Horstmann , Martin Gerhardt , Markus Forseberg
发明人： Christoph Schwan , Manfred Horstmann , Martin Gerhardt , Markus Forseberg
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L29/665
摘要： By recessing the isolation structure of a transistor prior to silicidation, the series resistance may be reduced due to the increased amount of metal silicide formed in the vicinity of the isolation structure. By recessing the isolation structure prior to the formation of the gate electrode, an increased degree of poly wrap around may be obtained, thereby increasing the effective channel width.
摘要翻译：通过在硅化之前使晶体管的隔离结构凹陷，由于在隔离结构附近形成的金属硅化物的量增加，串联电阻可能会降低。通过在形成栅电极之前使隔离结构凹陷，可以获得增加的聚环绕的程度，从而增加有效沟道宽度。

9. 发明授权

US09136177B2 Methods of forming transistor devices with high-k insulation layers and the resulting devices 有权
标题翻译：形成具有高k绝缘层的晶体管器件和所产生的器件的方法
公开(公告)号：US09136177B2
公开(公告)日：2015-09-15
申请号：US13561315
申请日：2012-07-30
申请人： Martin Gerhardt , Stefan Flachowsky , Matthias Kessler
发明人： Martin Gerhardt , Stefan Flachowsky , Matthias Kessler
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/3205 , H01L21/4763 , H01L21/8234 , H01L21/8238 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L27/088 , H01L21/28202 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).
摘要翻译：公开了形成晶体管器件的方法，其包括在第一和第二有源区之上形成第一层高k绝缘材料和牺牲保护层，从第二有源区上方去除第一绝缘材料层和保护层，去除所述保护层位于所述第一绝缘材料层上方，位于所述第一有源区上方，在所述第一绝缘材料层和所述第二有源区上方形成第二层高k绝缘材料，在所述第二层上方形成金属层的绝缘材料，并且去除第一和第二绝缘材料层和金属层的部分以形成第一栅极叠层（由第一和第二层高k材料和金属层组成）和第二栅极堆叠（由第二层高k材料和金属层组成）。

10. 发明申请

US20140070321A1 INTEGRATED CIRCUITS HAVING BORON-DOPED SILICON GERMANIUM CHANNELS AND METHODS FOR FABRICATING THE SAME 审中-公开
标题翻译：具有硼掺杂硅锗通道的集成电路及其制造方法
公开(公告)号：US20140070321A1
公开(公告)日：2014-03-13
申请号：US13613190
申请日：2012-09-13
申请人： Martin Gerhardt , Stefan Flachowsky , Matthias Kessler
发明人： Martin Gerhardt , Stefan Flachowsky , Matthias Kessler
IPC分类号： H01L27/088 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/4966 , H01L29/51 , H01L29/66651 , H01L29/7833
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. One method includes recessing a PFET active region to form a recessed PFET surface region. A boron-doped SiGe channel is formed overlying the recessed PFET surface region.
摘要翻译：提供了用于制造集成电路的集成电路和方法。一种方法包括凹陷PFET有源区以形成凹陷的PFET表面区域。在凹陷的PFET表面区域上形成掺杂硼的SiGe沟道。

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