专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08541885B2 Technique for enhancing transistor performance by transistor specific contact design 有权
标题翻译：通过晶体管特定接触设计增强晶体管性能的技术
公开(公告)号：US08541885B2
公开(公告)日：2013-09-24
申请号：US13107515
申请日：2011-05-13
申请人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
发明人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823871 , H01L23/485 , H01L29/41758 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
摘要翻译：通过局部地适应接触结构的尺寸和/或密度，例如，在单个晶体管内或以更全球化的方式，可以增加先进半导体器件的整体性能。因此，可以考虑接触结构和局部器件特性之间的相互作用。另一方面，可以保持与常规工艺策略的高度兼容性。

2. 发明申请

US20110215415A1 Technique for Enhancing Transistor Performance by Transistor Specific Contact Design 有权
标题翻译：通过晶体管特殊接触设计提高晶体管性能的技术
公开(公告)号：US20110215415A1
公开(公告)日：2011-09-08
申请号：US13107515
申请日：2011-05-13
申请人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
发明人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
IPC分类号： H01L27/092
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823871 , H01L23/485 , H01L29/41758 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
摘要翻译：通过局部地适应接触结构的尺寸和/或密度，例如，在单个晶体管内或以更全球化的方式，可以增加先进半导体器件的整体性能。因此，可以考虑接触结构和局部器件特性之间的相互作用。另一方面，可以保持与常规工艺策略的高度兼容性。

3. 发明授权

US07964970B2 Technique for enhancing transistor performance by transistor specific contact design 有权
标题翻译：通过晶体管特定接触设计增强晶体管性能的技术
公开(公告)号：US07964970B2
公开(公告)日：2011-06-21
申请号：US11964494
申请日：2007-12-26
申请人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
发明人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
IPC分类号： H01L29/40
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823871 , H01L23/485 , H01L29/41758 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
摘要翻译：通过局部地适应接触结构的尺寸和/或密度，例如，在单个晶体管内或以更全球化的方式，可以增加先进半导体器件的整体性能。因此，可以考虑接触结构和局部器件特性之间的相互作用。另一方面，可以保持与常规工艺策略的高度兼容性。

4. 发明申请

US20080265330A1 TECHNIQUE FOR ENHANCING TRANSISTOR PERFORMANCE BY TRANSISTOR SPECIFIC CONTACT DESIGN 有权
标题翻译：通过晶体管特殊接触设计提高晶体管性能的技术
公开(公告)号：US20080265330A1
公开(公告)日：2008-10-30
申请号：US11964494
申请日：2007-12-26
申请人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
发明人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
IPC分类号： H01L27/092
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823871 , H01L23/485 , H01L29/41758 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
摘要翻译：通过局部地适应接触结构的尺寸和/或密度，例如，在单个晶体管内或以更全球化的方式，可以增加先进半导体器件的整体性能。因此，可以考虑接触结构和局部器件特性之间的相互作用。另一方面，可以保持与常规工艺策略的高度兼容性。

5. 发明授权

US07994059B2 Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device 有权
标题翻译：通过在半导体器件中的双应力衬垫上方使用附加应力层来增强层间电介质中的应力转移
公开(公告)号：US07994059B2
公开(公告)日：2011-08-09
申请号：US11865796
申请日：2007-10-02
申请人： Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
发明人： Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
IPC分类号： H01L21/331
CPC分类号： H01L29/7833 , H01L21/76802 , H01L21/76825 , H01L21/76832 , H01L21/76837 , H01L21/823412 , H01L21/823807 , H01L27/092 , H01L29/7843
摘要： By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.
摘要翻译：通过在对具有不同的本征应力的介电衬垫进行图案化之后形成附加的应力介电材料，可以获得在晶体管中性能的显着提高，同时在高比例尺度的半导体器件中形成各个接触开口期间基本上不会构图不均匀性。附加介电层可以被提供任何类型的固有应力，而不管先前选择的图案化序列如何。

6. 发明申请

US20080179661A1 ENHANCED STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY USING AN ADDITIONAL STRESS LAYER ABOVE A DUAL STRESS LINER IN A SEMICONDUCTOR DEVICE 有权
标题翻译：通过在半导体器件中使用双应力衬垫上的附加应力层在中间层介质中增强应力传递
公开(公告)号：US20080179661A1
公开(公告)日：2008-07-31
申请号：US11865796
申请日：2007-10-02
申请人： Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
发明人： Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
IPC分类号： H01L29/78 , H01L21/469
CPC分类号： H01L29/7833 , H01L21/76802 , H01L21/76825 , H01L21/76832 , H01L21/76837 , H01L21/823412 , H01L21/823807 , H01L27/092 , H01L29/7843
摘要： By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.
摘要翻译：通过在对具有不同的本征应力的介电衬垫进行图案化之后形成附加的应力介电材料，可以获得在晶体管中性能的显着提高，同时在高比例尺度的半导体器件中形成各个接触开口期间基本上不会构图不均匀性。附加介电层可以被提供任何类型的固有应力，而不管先前选择的图案化序列如何。

7. 发明授权

US09034744B2 Replacement gate approach for high-k metal gate stacks by avoiding a polishing process for exposing the placeholder material 有权
标题翻译：通过避免用于暴露占位符材料的抛光工艺，用于高k金属栅极堆叠的替代栅极方法
公开(公告)号：US09034744B2
公开(公告)日：2015-05-19
申请号：US12942200
申请日：2010-11-09
申请人： Ralf Richter , Jens Heinrich , Andy Wei
发明人： Ralf Richter , Jens Heinrich , Andy Wei
IPC分类号： H01L29/772 , H01L21/8238 , H01L21/768 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/76819 , H01L21/823807 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7843
摘要： In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material.
摘要翻译：在替代栅极方法中，栅极电极结构的占位符材料的暴露可以基于蚀刻工艺来实现，从而避免引入与工艺相关的非均匀性，这通常与复杂的抛光工艺相关暴露占位符材料的顶面。在一些说明性实施例中，占位符材料可以通过基于牺牲掩模材料的蚀刻工艺曝光。

8. 发明授权

US08951907B2 Semiconductor devices having through-contacts and related fabrication methods 有权
标题翻译：具有通孔和相关制造方法的半导体器件
公开(公告)号：US08951907B2
公开(公告)日：2015-02-10
申请号：US12968068
申请日：2010-12-14
申请人： Ralf Richter , Jens Heinrich , Holger Schuehrer
发明人： Ralf Richter , Jens Heinrich , Holger Schuehrer
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/285 , H01L23/485
CPC分类号： H01L21/76808 , H01L21/28512 , H01L21/76802 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a layer of dielectric material overlying a doped region formed in a semiconductor substrate adjacent to a gate structure and forming a conductive contact in the layer of dielectric material. The conductive contact overlies and electrically connects to the doped region. The method continues by forming a second layer of dielectric material overlying the conductive contact, forming a voided region in the second layer overlying the conductive contact, forming a third layer of dielectric material overlying the voided region, and forming another voided region in the third layer overlying at least a portion of the voided region in the second layer. The method continues by forming a conductive material that fills both voided regions to contact the conductive contact.
摘要翻译：提供了半导体器件结构和相关制造方法的装置。一种用于制造半导体器件结构的方法包括形成覆盖在与栅极结构相邻的半导体衬底中形成的掺杂区域的介电材料层，并在该介电材料层中形成导电接触。导电接触覆盖并电连接到掺杂区域。该方法继续通过形成覆盖导电接触的第二层介电材料，在覆盖导电接触的第二层中形成空隙区域，形成覆盖空隙区域的第三层电介质材料，以及在第三层中形成另一个空隙区域覆盖第二层中的空隙区域的至少一部分。该方法通过形成填充两个空隙区域以接触导电触点的导电材料而继续。

9. 发明授权

US08697584B2 Enhanced transistor performance of N-channel transistors by using an additional layer above a dual stress liner in a semiconductor device 有权
标题翻译：通过在半导体器件中的双应力衬垫上方使用附加层来增强N沟道晶体管的晶体管性能
公开(公告)号：US08697584B2
公开(公告)日：2014-04-15
申请号：US12017175
申请日：2008-01-21
申请人： Ralf Richter , Andy Wei , Roman Boschke
发明人： Ralf Richter , Andy Wei , Roman Boschke
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L29/7843
摘要： By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor.
摘要翻译：通过在构成不同固有应力的介电衬垫的图案之后形成诸如氮化硅的附加电介质材料，可以获得N沟道晶体管的性能的显着提高，同时基本上不会导致P沟道晶体管的性能损失。

10. 发明申请

US20140048912A1 COMPRESSIVE STRESS TRANSFER IN AN INTERLAYER DIELECTRIC OF A SEMICONDUCTOR DEVICE BY PROVIDING A BI-LAYER OF SUPERIOR ADHESION AND INTERNAL STRESS 有权
标题翻译：通过提供超级粘合和内应力的双层来在半导体器件的中间层电介质中的压应力传递
公开(公告)号：US20140048912A1
公开(公告)日：2014-02-20
申请号：US13588460
申请日：2012-08-17
申请人： Joerg Hohage , Hartmut Ruelke , Ralf Richter
发明人： Joerg Hohage , Hartmut Ruelke , Ralf Richter
IPC分类号： H01L21/31 , H01L29/06
CPC分类号： H01L21/76832 , C23C16/345 , C23C16/45523 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/76834 , H01L21/823807 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.
摘要翻译：本公开提供了制造技术和半导体器件，其中可以基于涉及沉积介电双层系统的应力机制来增强P沟道晶体管的性能。与常规策略相反，可以在粘附层在无等离子体的工艺气氛中沉积之前进行另外的预处理，从而能够减小粘合层的厚度和随后的顶层的更高的内应力水平。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式