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    • 8. 发明授权
    • Parallel flash memory controller, chip and control method thereof
    • 并行闪存控制器,芯片及其控制方法
    • US08661188B2
    • 2014-02-25
    • US12599497
    • 2008-05-05
    • He Huang
    • He Huang
    • G06F12/00
    • G06F13/4239
    • A parallel flash memory controller, a chip, and a control method thereof are disclosed. First, an on-chip control bus sends flash memory control instructions in parallel to instruction parsing units (211) according to channels. Next, the instruction parsing units store (211) and parse the flash memory instructions corresponding to the flash memory channels, and sequentially send the flash memory control instruction to the flash memory control units (213). Then, the flash memory control units (213) send control instructions to the flash chips in the channels according to rows, and then the control instructions are processed in parallel in flash memory rows. In the present invention, the operations for each channel are performed independently in parallel, the flash memory control units (213) in the channels send the control instructions in series, and meanwhile, in each flash memory row, operations are concurrently performed in parallel. Therefore, the read/write rate of the flash memory is increased for many times, and the bottleneck in adopting flash memory chips to accomplish high-speed and large-capacity storage devices is effectively eliminated.
    • 公开了并行闪存控制器,芯片及其控制方法。 首先,片上控制总线根据信道将指令解析单元(211)并行发送闪存控制指令。 接下来,指令解析单元存储(211)并解析对应于闪存通道的闪存指令,并且将闪存控制指令顺序地发送到闪速存储器控制单元(213)。 然后,闪速存储器控制单元(213)根据行将控制指令发送到通道中的闪存芯片,然后控制指令在闪存存储器行中并行处理。 在本发明中,并行地进行各信道的动作,通道中的闪速存储器控制部(213)串联发送控制指令,同时在每个闪速存储器行中并行并行执行操作。 因此,闪速存储器的读/写速率增加了许多次,并且有效地消除了采用闪存芯片来实现高速和大容量存储设备的瓶颈。