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1. 发明授权

US07479458B1 Methods and apparatus for the optimization of highly selective process gases 有权
标题翻译：用于优化高选择性工艺气体的方法和设备
公开(公告)号：US07479458B1
公开(公告)日：2009-01-20
申请号：US11305369
申请日：2005-12-15
申请人： Guang-Yaw Hwang , Thomas Nguyen , Wen-Ben Chou , Timothy Tran , Yu-Wei Yang
发明人： Guang-Yaw Hwang , Thomas Nguyen , Wen-Ben Chou , Timothy Tran , Yu-Wei Yang
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/76811 , H01L21/76813
摘要： A method for etching a barrier material on a semiconductor substrate is disclosed. The method includes placing the substrate in a plasma processing chamber of the plasma processing system, wherein the substrate includes the barrier material and a low-k material, and wherein the barrier material and a low-k material are configured to be exposed to a plasma. The method also includes flowing an etchant gas mixture, including CH3F from about 4% to about 8% of a plasma gas flow, into the plasma processing chamber, wherein the etchant gas mixture is configured to etch the barrier material at a first etch rate, the etchant gas mixture is configured to etch the low-k material at a second etch rate, wherein the first etch rate is substantially greater than the second etch rate. The method further includes striking a plasma from the etchant source gas; and etching the barrier layer and the low-k layer.
摘要翻译：公开了一种在半导体衬底上蚀刻阻挡材料的方法。该方法包括将衬底放置在等离子体处理系统的等离子体处理室中，其中衬底包括阻挡材料和低k材料，并且其中阻挡材料和低k材料构造成暴露于等离子体。该方法还包括将包括等离子体气体流的约4％至约8％的CH 3 F的蚀刻剂气体混合物流入等离子体处理室，其中蚀刻剂气体混合物被配置为以第一蚀刻速率蚀刻阻挡材料，蚀刻剂气体混合物被配置为以第二蚀刻速率蚀刻低k材料，其中第一蚀刻速率基本上大于第二蚀刻速率。该方法还包括从蚀刻剂源气体冲击等离子体; 并蚀刻阻挡层和低k层。

2. 发明授权

US06977184B1 Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring 失效
标题翻译：用于氮化物间隔物蚀刻工艺的方法和装置，其实现原位干涉测量终点检测和非干涉测量终点监测
公开(公告)号：US06977184B1
公开(公告)日：2005-12-20
申请号：US09998858
申请日：2001-10-31
申请人： Wen-Ben Chou , Shih-Yuan Cheng , Wayne Tu
发明人： Wen-Ben Chou , Shih-Yuan Cheng , Wayne Tu
IPC分类号： H01J37/32 , H01L21/311 , H01L21/8234 , H01L21/302
CPC分类号： H01J37/3244 , H01L21/31116 , H01L21/823468
摘要： A method for fabricating a spacer of a gate structure is provided. The method performing a first etch process implementing a first etchant gas. The first etch process is configured to implement an interferometry endpoint (IEP) detection method to detect a removal of a portion of a spacer layer having a specific thickness from over the surface of the substrate, thus leaving a thin spacer layer. The method further includes performing a second etch process for a predetermined period of time implementing a second etchant gas. The second etch process is configured to remove the thin spacer layer, leaving the spacer for the gate structure.
摘要翻译：提供一种用于制造栅极结构的间隔物的方法。该方法执行实施第一蚀刻剂气体的第一蚀刻工艺。第一蚀刻工艺被配置为实现干涉测量终点（IEP）检测方法，以检测从衬底的表面上去除具有特定厚度的间隔层的一部分，从而留下薄的间隔层。该方法还包括在实施第二蚀刻剂气体的预定时间段内执行第二蚀刻工艺。第二蚀刻工艺被配置为去除薄间隔层，留下用于栅极结构的间隔物。

3. 发明授权

US5904571A Methods and apparatus for reducing charging during plasma processing 失效
标题翻译：等离子体处理过程中减少充电的方法和装置
公开(公告)号：US5904571A
公开(公告)日：1999-05-18
申请号：US671872
申请日：1996-06-28
申请人： Roger Patrick , Phillip L. Jones , Kambiz Fallahpour , Yun-Yen Yang , Wen-Ben Chou
发明人： Roger Patrick , Phillip L. Jones , Kambiz Fallahpour , Yun-Yen Yang , Wen-Ben Chou
IPC分类号： H01J37/32 , H01L21/00 , H05H1/00
CPC分类号： H01J37/32431 , H01J2237/004
摘要： An apparatus and method in a plasma processing chamber for reducing charging of a wafer is described. A plasma generating element is configured to cause a plasma including ions and free radicals to be formed in a plasma generating region. A plasma diffusion region is configured so that plasma generated in the plasma generating region can diffuse through the plasma diffusion region. A conductive grid is positioned within the plasma diffusion region between the wafer and the plasma generating region. The conductive grid includes a mesh which is configured to trap a portion of the ions so that a portion of the ions are prevented from diffusing through the diffusion region to reach the wafer.
摘要翻译：描述了用于减少晶片充电的等离子体处理室中的装置和方法。等离子体产生元件构造成在等离子体产生区域中形成包含离子和自由基的等离子体。等离子体扩散区域被配置为使得在等离子体产生区域中产生的等离子体可以扩散通过等离子体扩散区域。导电栅格位于晶片和等离子体产生区域之间的等离子体扩散区域内。导电栅格包括网孔，其被配置为捕获一部分离子，使得一部分离子被阻止通过扩散区扩散到达晶片。

4. 发明申请

US20060040415A1 Method and apparatus for nitride spacer etch process implementing in situ interferometry endpoint detection and non-interferometry endpoint monitoring 审中-公开
标题翻译：用于氮化物间隔物蚀刻工艺的方法和装置，其实现原位干涉测量终点检测和非干涉测量终点监测
公开(公告)号：US20060040415A1
公开(公告)日：2006-02-23
申请号：US11258658
申请日：2005-10-25
申请人： Wen-Ben Chou , Shih-Yuan Cheng , Wayne Tu
发明人： Wen-Ben Chou , Shih-Yuan Cheng , Wayne Tu
IPC分类号： H01L21/00 , C23F1/00
CPC分类号： H01J37/3244 , H01L21/31116 , H01L21/823468
摘要： An in situ dual-stage etch endpoint detection system is disclosed. The system includes an etch chamber, an interferometry endpoint monitoring system, and a non-IEP endpoint monitoring system. The etch chamber includes an electrostatic chuck (ESC), a top electrode, and a bottom electrode. The ESC is designed to support a wafer having a spacer layer formed over a gate structure. The interferometry endpoint (IEP) monitoring system is designed to monitor an interference photon beam reflected by the top of spacer layer and the reflection beam on interface of bottom of spacer during a first etch operation. The non-IEP endpoint monitoring system monitors a second etch operation by monitoring an etch time. A first etch operation implementing the IEP monitoring system is discontinued, leaving a thin spacer layer to be etched during the second etch operation.
摘要翻译：公开了原位双级蚀刻终点检测系统。该系统包括蚀刻室，干涉测量终点监测系统和非IEP端点监测系统。蚀刻室包括静电卡盘（ESC），顶部电极和底部电极。 ESC被设计成支撑在栅极结构上形成间隔层的晶片。干涉测量终点（IEP）监测系统设计用于在第一次蚀刻操作期间监测由间隔层的顶部反射的干涉光子束和隔离物底部界面上的反射光束。非IEP端点监测系统通过监测蚀刻时间来监测第二蚀刻操作。停止实施IEP监测系统的第一蚀刻操作，留下在第二蚀刻操作期间被蚀刻的薄间隔层。

5. 发明授权

US06337277B1 Clean chemistry low-k organic polymer etch 有权
标题翻译：清洁化学低k有机聚合物蚀刻
公开(公告)号：US06337277B1
公开(公告)日：2002-01-08
申请号：US09606842
申请日：2000-06-28
申请人： Wen-Ben Chou , Rajinder Dhindsa , Ching-Hwa Chen
发明人： Wen-Ben Chou , Rajinder Dhindsa , Ching-Hwa Chen
IPC分类号： H01L21302
CPC分类号： H01L21/31138
摘要： A method of cleanly etching an organic polymer layer disposed over a substrate is disclosed. The invention is particularly useful in damascene processing where openings are etched in the organic polymer layer to form interconnects. The method includes lowering the temperature of the substrate. The method also includes flowing H2O vapor over the organic polymer layer and condensing (or freezing) the H2O vapor on the organic polymer layer. The method additionally includes etching through the organic polymer layer and the condensed H2O vapor to form an opening having a side wall. The condensed (or frozen) H2O vapor is arranged to form a passivating film (of ice) along the side wall of the opening to protect the side wall from etching.
摘要翻译：公开了一种干净地蚀刻位于衬底上的有机聚合物层的方法。本发明特别适用于在有机聚合物层中蚀刻开口以形成互连的镶嵌加工中。该方法包括降低基板的温度。该方法还包括将H 2 O蒸气流过有机聚合物层并将H 2 O蒸气冷凝（或冷冻）在有机聚合物层上。该方法还包括通过有机聚合物层和冷凝的H 2 O蒸气蚀刻以形成具有侧壁的开口。冷凝（或冷冻的）H 2 O蒸气被布置成沿着开口的侧壁形成钝化膜（冰），以保护侧壁免受蚀刻。

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