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1. 发明授权

US09075600B2 Program status word dependency handling in an out of order microprocessor design 有权
标题翻译：程序状态字依赖处理在一个无序的微处理器设计
公开(公告)号：US09075600B2
公开(公告)日：2015-07-07
申请号：US12822974
申请日：2010-06-24
申请人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
发明人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30101 , G06F9/3838 , G06F9/384
摘要： A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
摘要翻译：一种处理计算机程序指令的计算机实现方法。该方法包括提供程序状态数据的至少两个副本; 识别写入所述程序状态数据的至少一个字段的所述指令的第一更新指令; 以及将所述第一更新指令与所述至少两个程序状态数据副本的第一副本相关联。

2. 发明申请

US20110320782A1 PROGRAM STATUS WORD DEPENDENCY HANDLING IN AN OUT OF ORDER MICROPROCESSOR DESIGN 有权
标题翻译：程序状态字依赖于处理订单微处理器设计
公开(公告)号：US20110320782A1
公开(公告)日：2011-12-29
申请号：US12822974
申请日：2010-06-24
申请人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
发明人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
IPC分类号： G06F9/318
CPC分类号： G06F9/30101 , G06F9/3838 , G06F9/384
摘要： A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
摘要翻译：一种处理计算机程序指令的计算机实现方法。该方法包括提供程序状态数据的至少两个副本; 识别写入所述程序状态数据的至少一个字段的所述指令的第一更新指令; 以及将所述第一更新指令与所述至少两个程序状态数据副本的第一副本相关联。

3. 发明申请

US20130339666A1 SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION 审中-公开
公开(公告)号：US20130339666A1
公开(公告)日：2013-12-19
申请号：US13524471
申请日：2012-06-15
申请人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
发明人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30043 , G06F9/3017 , G06F9/384
摘要： A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag.

4. 发明申请

US20090217009A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS 有权
标题翻译：用于转储储存元件的系统，方法和计算机程序产品
公开(公告)号：US20090217009A1
公开(公告)日：2009-08-27
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/318
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

5. 发明申请

US20090240921A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SUPPORTING PARTIAL RECYCLE IN A PIPELINED MICROPROCESSOR 有权
标题翻译：用于支持管道微处理器部分回收的方法，系统和计算机程序产品
公开(公告)号：US20090240921A1
公开(公告)日：2009-09-24
申请号：US12051486
申请日：2008-03-19
申请人： Khary J. Alexander , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei
发明人： Khary J. Alexander , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei
IPC分类号： G06F9/30
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3842
摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.
摘要翻译：提供了一种计算机处理系统。计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。

6. 发明授权

US07966474B2 System, method and computer program product for translating storage elements 有权
标题翻译：用于翻译存储元件的系统，方法和计算机程序产品
公开(公告)号：US07966474B2
公开(公告)日：2011-06-21
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/26
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

7. 发明授权

US08516228B2 Supporting partial recycle in a pipelined microprocessor 有权
标题翻译：支持流水线微处理器的部分回收
公开(公告)号：US08516228B2
公开(公告)日：2013-08-20
申请号：US12051486
申请日：2008-03-19
申请人： Khary J. Alexander , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei
发明人： Khary J. Alexander , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei
IPC分类号： G06F9/00
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3842
摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.
摘要翻译：提供了一种计算机处理系统。计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。

8. 发明授权

US08201067B2 Processor error checking for instruction data 有权
标题翻译：处理器错误检查指令数据
公开(公告)号：US08201067B2
公开(公告)日：2012-06-12
申请号：US12037038
申请日：2008-02-25
申请人： Fadi Y. Busaba , Khary J. Alexander , Michael Billeci , Bruce C. Giamei , Vimal M. Kapadia
发明人： Fadi Y. Busaba , Khary J. Alexander , Michael Billeci , Bruce C. Giamei , Vimal M. Kapadia
IPC分类号： G06F11/00 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： G06F11/10
摘要： A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.
摘要翻译：一种用于处理器错误检查的方法，包括接收指令数据，基于指令数据产生预处理奇偶校验数据，维持预处理奇偶校验数据，处理指令数据，基于处理指令产生后处理奇偶校验数据数据，通过将后处理奇偶校验数据与预处理奇偶校验数据进行比较来检查与处理指令数据相关的错误，以及如果后处理奇偶校验数据发送指示与处理指令数据相关的错误的错误信号数据与预处理奇偶校验数据不匹配，其中在不使用重复处理电路的情况下执行检查与处理指令数据有关的错误。

9. 发明申请

US20090217077A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PROCESSOR ERROR CHECKING 有权
标题翻译：用于处理器错误检查的方法，系统和计算机程序产品
公开(公告)号：US20090217077A1
公开(公告)日：2009-08-27
申请号：US12037038
申请日：2008-02-25
申请人： Fadi Y. Busaba , Khary J. Alexander , Michael Billeci , Bruce C. Giamei , Vimal M. Kapadia
发明人： Fadi Y. Busaba , Khary J. Alexander , Michael Billeci , Bruce C. Giamei , Vimal M. Kapadia
IPC分类号： G06F11/07
CPC分类号： G06F11/10
摘要： A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.
摘要翻译：一种用于处理器错误检查的方法，包括接收指令数据，基于指令数据产生预处理奇偶校验数据，维持预处理奇偶校验数据，处理指令数据，基于处理指令产生后处理奇偶校验数据数据，通过将后处理奇偶校验数据与预处理奇偶校验数据进行比较来检查与处理指令数据相关的错误，以及如果后处理奇偶校验数据发送指示与处理指令数据相关的错误的错误信号数据与预处理奇偶校验数据不匹配，其中在不使用重复处理电路的情况下执行检查与处理指令数据有关的错误。

10. 发明授权

US08090933B2 Methods computer program products and systems for unifying program event recording for branches and stores in the same dataflow 有权
标题翻译：方法计算机程序产品和系统，用于在同一数据流中统一分支和存储的程序事件记录
公开(公告)号：US08090933B2
公开(公告)日：2012-01-03
申请号：US12029696
申请日：2008-02-12
申请人： Fadi Y. Busaba , Bruce C. Giamei
发明人： Fadi Y. Busaba , Bruce C. Giamei
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/322 , G06F9/30043 , G06F9/3005
摘要： The present invention relates to a method for the unification of PER branch and PER store operations within the same dataflow. The method comprises determining a PER range, the PER range comprising a storage area defined by a designated storage starting area and a designated storage ending area, wherein the storage starting area is designated by a value of the contents of a first control register and the storage ending area is designated by a value of the contents of a second control register. The method also comprises retrieving register field content values that are stored at a plurality of registers, wherein the retrieved content values comprises a length field content value, and setting the length field content value to zero for a PER branch instruction, thereby enabling a PER branch instruction to performed similarly to a PER storage instruction.
摘要翻译：本发明涉及在同一数据流内统一PER分支和PER存储操作的方法。该方法包括：确定PER范围，所述PER范围包括由指定的存储开始区域和指定的存储结束区域定义的存储区域，其中所述存储起始区域由第一控制寄存器的内容的值指定，结束区域由第二控制寄存器的内容的值指定。该方法还包括检索存储在多个寄存器中的寄存器字段内容值，其中所检索的内容值包括长度字段内容值，并且对于PER分支指令将长度字段内容值设置为零，从而使得PER分支执行与PER存储指令类似的指令。

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