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1. 发明申请

US20070139864A1 Embedded capacitors and methods for their fabrication and connection 失效
标题翻译：嵌入式电容器及其制造和连接方法
公开(公告)号：US20070139864A1
公开(公告)日：2007-06-21
申请号：US11316087
申请日：2005-12-21
申请人： Gregory Dunn , Remy Chelini , Robert Croswell , Philip Lessner , Michael Prevallet , John Prymak
发明人： Gregory Dunn , Remy Chelini , Robert Croswell , Philip Lessner , Michael Prevallet , John Prymak
IPC分类号： H01G9/00
CPC分类号： H01G9/045 , H01G9/0032 , H01G9/055 , H01G9/15 , H05K1/162 , H05K3/383 , H05K3/429 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718 , H05K2203/0315
摘要： Embedded capacitors comprise a bimetal foil (500) that includes a first copper layer (205) and an aluminum layer (210) on the first copper layer. The aluminum layer has a smooth side adjacent the first copper layer and a high surface area textured side (215) opposite the first copper layer. The bimetal foil further includes an aluminum oxide layer (305) on the high surface area textured side of the aluminum layer, a conductive polymerlayer (420) on the aluminum oxide layer, and a second copper layer (535) overlying the aluminum oxide layer. The bimetal foil may be embedded in a circuit board (700) to form high value embedded capacitors.
摘要翻译：嵌入式电容器包括在第一铜层上包括第一铜层（205）和铝层（210）的双金属箔（500）。铝层具有邻近第一铜层的平滑侧面和与第一铜层相对的高表面积纹理化侧面（215）。双金属箔还包括在铝层的高表面积纹理化侧的氧化铝层（305），氧化铝层上的导电聚合物层（420）和覆盖在氧化铝层上的第二铜层（535）。双金属箔可以嵌入在电路板（700）中以形成高价值的嵌入式电容器。

2. 发明申请

US20050135074A1 Printed circuit dielectric foil and embedded capacitors 失效
标题翻译：印刷电路介质箔和嵌入式电容器
公开(公告)号：US20050135074A1
公开(公告)日：2005-06-23
申请号：US10744695
申请日：2003-12-23
申请人： Gregory Dunn , Remy Chelini , Robert Croswell , Timothy Dean , Claudia Gamboa , Jovica Savic
发明人： Gregory Dunn , Remy Chelini , Robert Croswell , Timothy Dean , Claudia Gamboa , Jovica Savic
IPC分类号： H05K1/16 , H05K3/02 , H05K3/42
CPC分类号： H05K1/162 , H05K3/025 , H05K3/429 , H05K2201/0175 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718
摘要： A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).
摘要翻译：电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414），664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器， / SUP>）。

3. 发明申请

US20070139294A1 High impedance electromagnetic surface and method 失效
标题翻译：高阻抗电磁表面和方法
公开(公告)号：US20070139294A1
公开(公告)日：2007-06-21
申请号：US11312286
申请日：2005-12-20
申请人： Gregory Dunn , Robert Croswell , George Kumpf , John Svigelj
发明人： Gregory Dunn , Robert Croswell , George Kumpf , John Svigelj
IPC分类号： H01Q15/24
CPC分类号： H01Q15/006 , H05K1/116 , H05K1/162 , H05K1/165 , H05K3/429 , H05K3/4602 , H05K3/4688 , H05K2201/0187 , H05K2201/0715 , H05K2201/09509 , H05K2201/09609
摘要： A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates , wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).
摘要翻译：高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319）电路板（302）。多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器在印刷电路板（302）内。

4. 发明申请

US20060207970A1 Printed circuit patterned embedded capacitance layer 失效
标题翻译：印刷电路图案化嵌入式电容层
公开(公告)号：US20060207970A1
公开(公告)日：2006-09-21
申请号：US11084938
申请日：2005-03-21
申请人： Gregory Dunn , Robert Croswell , Jaroslaw Magera , Jovica Savic , Aroon Tungare
发明人： Gregory Dunn , Robert Croswell , Jaroslaw Magera , Jovica Savic , Aroon Tungare
IPC分类号： B44C1/22 , C23F1/00
CPC分类号： C23F1/40 , C23F1/02 , C23F1/32 , C23F1/34 , H05K1/162 , H05K3/0044 , H05K3/025 , H05K3/06 , H05K3/429 , H05K2201/0175 , H05K2201/0179 , H05K2201/09309 , H05K2201/09509 , H05K2203/025 , H05K2203/0746
摘要： A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.
摘要翻译：公开了一种用于制造图案化的嵌入式电容层的方法。该方法包括制造覆盖在印刷电路衬底（505）上的导电金属层（515）上的陶瓷氧化物层（510），在区域（705）内穿孔（1320）陶瓷氧化物层，以及去除（1325）通过化学蚀刻导电金属层的区域中的陶瓷氧化物层和导电金属层。陶瓷氧化物层可以小于1微米厚。

5. 发明申请

US20050128720A1 Printed circuit embedded capacitors 失效
标题翻译：印刷电路嵌入式电容器
公开(公告)号：US20050128720A1
公开(公告)日：2005-06-16
申请号：US10736327
申请日：2003-12-15
申请人： Robert Croswell , Gregory Dunn , Robert Lempkowski , Aroon Tungare , Jovica Savic
发明人： Robert Croswell , Gregory Dunn , Robert Lempkowski , Aroon Tungare , Jovica Savic
IPC分类号： H01G20060101 , H05K1/16 , H05K3/00 , H05K3/02 , H05K3/42 , H05K3/46 , H05K7/06
CPC分类号： H05K1/162 , H05K3/0029 , H05K3/025 , H05K3/384 , H05K3/429 , H05K3/4652 , H05K2201/0175 , H05K2201/0179 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718
摘要： One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.
摘要翻译：嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm 2。多个电容器的材料和厚度相同。结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

6. 发明授权

US06638872B1 Integration of monocrystalline oxide devices with fully depleted CMOS on non-silicon substrates 失效
标题翻译：在非硅衬底上集成具有完全耗尽CMOS的单晶氧化物器件
公开(公告)号：US06638872B1
公开(公告)日：2003-10-28
申请号：US10255881
申请日：2002-09-26
申请人： Robert Croswell , Gregory Dunn
发明人： Robert Croswell , Gregory Dunn
IPC分类号： H01L21311
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/02488 , H01L21/02505 , H01L21/02513 , H01L21/02521 , H01L21/76254 , H01L21/84 , H01L27/0605 , H01L27/12 , H01L29/78603
摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. Monocrystalline substrates having a hydrogen ion implant are cleaved along the hydrogen ion implant, and an insulating substrate is bonded to the monocrystalline oxide.
摘要翻译：通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。此外，顺应性衬底的形成可以包括利用表面活性剂增强的单晶硅在单晶氧化物材料上的外延和外延生长。具有氢离子注入的单晶衬底沿氢离子注入被切割，绝缘衬底与单晶氧化物结合。

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