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1. 发明申请

US20050135074A1 Printed circuit dielectric foil and embedded capacitors 失效
标题翻译：印刷电路介质箔和嵌入式电容器
公开(公告)号：US20050135074A1
公开(公告)日：2005-06-23
申请号：US10744695
申请日：2003-12-23
申请人： Gregory Dunn , Remy Chelini , Robert Croswell , Timothy Dean , Claudia Gamboa , Jovica Savic
发明人： Gregory Dunn , Remy Chelini , Robert Croswell , Timothy Dean , Claudia Gamboa , Jovica Savic
IPC分类号： H05K1/16 , H05K3/02 , H05K3/42
CPC分类号： H05K1/162 , H05K3/025 , H05K3/429 , H05K2201/0175 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718
摘要： A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).
摘要翻译：电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414），664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器， / SUP>）。

2. 发明申请

US20070209178A1 METHOD FOR FORMING EMBEDDED CAPACITORS ON A PRINTED CURCUIT BOARD AND RESULTANT PRINTED CIRCUIT BOARD 失效
标题翻译：在印刷电路板和印刷电路板上形成嵌入式电容器的方法
公开(公告)号：US20070209178A1
公开(公告)日：2007-09-13
申请号：US11276688
申请日：2006-03-10
申请人： Jovica Savic , Remy Chelini , Gregory Dunn
发明人： Jovica Savic , Remy Chelini , Gregory Dunn
IPC分类号： H01G7/00 , H01K3/10
CPC分类号： H01G4/33 , H01G4/12 , H05K1/162 , H05K3/0044 , H05K2201/0175 , H05K2201/0187 , H05K2201/0195 , H05K2201/0209 , H05K2201/09509 , H05K2203/025 , Y10T29/417 , Y10T29/43 , Y10T29/435 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.
摘要翻译：公开了一种在印刷电路板上形成嵌入式电容器的方法。通过在位于PCB上的一个或多个电极上沉积第一介电层，在印刷电路板上形成电容器。另一电极形成在第一电介质层的顶部，并且第二电介质层沉积在该电极的顶部上。在第二电介质层的顶部形成第三电极。通过诸如喷砂的方法在单个步骤中擦拭两个电介质层，以限定第一和第二电介质层的部分以产生多层电容结构。

3. 发明申请

US20050128720A1 Printed circuit embedded capacitors 失效
标题翻译：印刷电路嵌入式电容器
公开(公告)号：US20050128720A1
公开(公告)日：2005-06-16
申请号：US10736327
申请日：2003-12-15
申请人： Robert Croswell , Gregory Dunn , Robert Lempkowski , Aroon Tungare , Jovica Savic
发明人： Robert Croswell , Gregory Dunn , Robert Lempkowski , Aroon Tungare , Jovica Savic
IPC分类号： H01G20060101 , H05K1/16 , H05K3/00 , H05K3/02 , H05K3/42 , H05K3/46 , H05K7/06
CPC分类号： H05K1/162 , H05K3/0029 , H05K3/025 , H05K3/384 , H05K3/429 , H05K3/4652 , H05K2201/0175 , H05K2201/0179 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718
摘要： One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.
摘要翻译：嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm 2。多个电容器的材料和厚度相同。结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

4. 发明申请

US20060207970A1 Printed circuit patterned embedded capacitance layer 失效
标题翻译：印刷电路图案化嵌入式电容层
公开(公告)号：US20060207970A1
公开(公告)日：2006-09-21
申请号：US11084938
申请日：2005-03-21
申请人： Gregory Dunn , Robert Croswell , Jaroslaw Magera , Jovica Savic , Aroon Tungare
发明人： Gregory Dunn , Robert Croswell , Jaroslaw Magera , Jovica Savic , Aroon Tungare
IPC分类号： B44C1/22 , C23F1/00
CPC分类号： C23F1/40 , C23F1/02 , C23F1/32 , C23F1/34 , H05K1/162 , H05K3/0044 , H05K3/025 , H05K3/06 , H05K3/429 , H05K2201/0175 , H05K2201/0179 , H05K2201/09309 , H05K2201/09509 , H05K2203/025 , H05K2203/0746
摘要： A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.
摘要翻译：公开了一种用于制造图案化的嵌入式电容层的方法。该方法包括制造覆盖在印刷电路衬底（505）上的导电金属层（515）上的陶瓷氧化物层（510），在区域（705）内穿孔（1320）陶瓷氧化物层，以及去除（1325）通过化学蚀刻导电金属层的区域中的陶瓷氧化物层和导电金属层。陶瓷氧化物层可以小于1微米厚。

5. 发明申请

US20050133872A1 Two-layer patterned resistor 失效
标题翻译：双层图案电阻
公开(公告)号：US20050133872A1
公开(公告)日：2005-06-23
申请号：US10743589
申请日：2003-12-22
申请人： Gregory Dunn , Scott Carney , Jovica Savic
发明人： Gregory Dunn , Scott Carney , Jovica Savic
IPC分类号： H01C1/148 , H01C7/00 , H01C17/065 , H01L21/8222 , H01L23/498 , H01L23/62
CPC分类号： H01C7/006 , H01C1/148 , H01C17/065 , H01L23/49822 , H01L2924/0002 , H01L2924/00
摘要： A technique for fabricating a patterned resistor on a substrate produces a patterned resistor (101, 801, 1001, 1324, 1374) including two conductive end terminations (110, 810, 1010) on the substrate, a pattern of first resistive material (120, 815, 1015) having a first width (125) and a first sheet resistance, and a pattern of second resistive material (205, 820, 1020) having a second width (210) and a second sheet resistance that at least partially overlies the pattern of first resistive material. One of the first and second sheet resistances is a low sheet resistance and the other of the first and second resistances is a high sheet resistance. A ratio of the high sheet resistance to the low sheet resistance is at least ten to one. The pattern having the higher sheet resistance is substantially wider than the pattern having the low sheet resistance. The patterned resistor can be precision trimmed 1225.
摘要翻译：用于在衬底上制造图案化电阻器的技术产生包括在衬底上的两个导电端接（110,810,1010）的图案化电阻器（101,801,1001,1324,1374），第一电阻材料（120，具有第一宽度（125）和第一薄层电阻的第二电阻材料（205,820,1020）的图案，以及具有至少部分地覆盖图案的第二宽度（210）和第二薄层电阻的图案的第一电阻材料。第一和第二薄层电阻之一是低的薄层电阻，第一和第二电阻中的另一个是高的薄层电阻。高薄层电阻与低薄层电阻的比例至少为10比1。具有较高薄层电阻的图案基本上比具有低薄层电阻的图案更宽。图案化电阻器可精密修整1225。

6. 发明申请

US20050242997A1 Dielectric sheet, method for fabricating the dielectric sheet, printed circuit and patch antenna using the dielectric sheet, and method for fabricating the printed circuit 失效
标题翻译：电介质片，用于制造电介质片的方法，使用电介质片的印刷电路和贴片天线以及制造印刷电路的方法
公开(公告)号：US20050242997A1
公开(公告)日：2005-11-03
申请号：US10837461
申请日：2004-04-30
申请人： Gregory Dunn , Jeffrey Petsinger , Jovica Savic
发明人： Gregory Dunn , Jeffrey Petsinger , Jovica Savic
IPC分类号： H01G2/12 , H05K1/03 , H05K1/16 , H05K3/00 , H05K3/06 , H05K3/42
CPC分类号： H05K3/0023 , H05K1/0366 , H05K1/162 , H05K3/064 , H05K3/429 , H05K2201/0175 , H05K2201/0355 , H05K2201/09309 , H05K2203/0571
摘要： A dielectric sheet (500, 600, 1621) includes a photodielectric support layer (505, 1630) that may be glass reinforced and a dielectric laminate (510, 605). The dielectric laminate includes first and second metal foil layers (415, 660; 210, 665, 1605, 1610), and a dielectric layer (405, 655, 1620) disposed between the first and second metal foil layers. The first metal foil layer is adhered to the photodielectric support layer. In a printed circuit and patch antenna that includes the dielectric sheet, the first metal layer is patterned by removal of metal according to a circuit pattern and the photodielectric support layer is patterned by removal of dielectric material according to the circuit pattern.
摘要翻译：电介质片（500,600,1621）包括可以被玻璃增强的光电介质支撑层（505,1630）和介电层压板（510,605）。介电层压板包括设置在第一和第二金属箔层之间的第一和第二金属箔层（415,660; 210,665,1605,1610）和介电层（405,655,1620）。第一金属箔层粘附到光致介电支撑层上。在包括电介质片的印刷电路和贴片天线中，通过根据电路图案去除金属来对第一金属层进行构图，并且通过根据电路图案去除介电材料来对光致介电支撑层进行图案化。

7. 发明申请

US20070151758A1 Capacitance laminate and printed circuit board apparatus and method 失效
标题翻译：电容层压板和印刷电路板装置及方法
公开(公告)号：US20070151758A1
公开(公告)日：2007-07-05
申请号：US11323515
申请日：2005-12-30
申请人： Gregory Dunn , Jaroslaw Magera , Jovica Savic
发明人： Gregory Dunn , Jaroslaw Magera , Jovica Savic
IPC分类号： H05K1/11 , H01R12/04
CPC分类号： H05K1/162 , H05K3/429 , H05K3/4602 , H05K3/4652 , H05K2201/0175 , H05K2201/09309 , H05K2201/09509 , H05K2201/09536 , H05K2201/09718
摘要： A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.
摘要翻译：一种用于制造嵌入式电容印刷电路板组件（400,1100）的方法。嵌入式电容印刷电路板组件包括两个嵌入式电容结构（110）。每个电容结构（110）包括夹在两个内部电极层电连接在一起的外部电极层（120）和内部电极层（125）之间的结晶化电介质氧化物层（115）。可以使用铆钉通孔（1315）和由按钮通孔（910）和堆叠的通孔（1111）形成的堆叠通孔（1110）将两个内部电极层电连接在一起。主轴通孔（525）可以通过内层和外层形成。多层印刷电路板可以由包括两个电容结构的电容层压板（100）形成。

8. 发明申请

US20060137173A1 Textured dielectric and patch antenna fabrication method 失效
标题翻译：纹理电介质和贴片天线制造方法
公开(公告)号：US20060137173A1
公开(公告)日：2006-06-29
申请号：US11021444
申请日：2004-12-23
申请人： Gregory Dunn , Jovica Savic , John Svigelj , Nadia Yala
发明人： Gregory Dunn , Jovica Savic , John Svigelj , Nadia Yala
IPC分类号： H01P11/00 , H01K3/10
CPC分类号： H01Q9/0407 , Y10T29/49016 , Y10T29/49117 , Y10T29/49165
摘要： A textured dielectric panel (305, 520, 625, 745, 925, 1035, 1205) is fabricated by applying a first mask pattern (310, 510, 610, 710, 915, 1015, 1210) to a first side of a solid panel made of a first material that is a ceramic dielectric and then sandblasting the solid panel through the first mask pattern from the first side to at least partially generate a shaped cavity (315, 920, 1040). The shaped cavity of the solid panel may be filled with a-second material (330, 740). The first and second materials have substantially differing dielectric constants. The first side and second side of the solid panel may be metallized (325), forming a patch antenna. The shaped cavities can be made more complex by using additional masking and/or sandblasting steps.
摘要翻译：通过将第一掩模图案（310,510,610,710,915,1015,1210）施加到固体面板的第一侧来制造纹理化电介质面板（305,520,625,745,925,1035,1205）由第一材料制成，其是陶瓷电介质，然后通过第一掩模图案从第一侧喷砂固体板，以至少部分地产生成型腔（315,920,1040）。固体面板的成形腔可以填充有第二材料（330,740）。第一和第二材料具有基本上不同的介电常数。固体面板的第一面和第二面可以金属化（325），形成贴片天线。通过使用额外的掩模和/或喷砂步骤，可使成形的空腔变得更加复杂。

9. 发明授权

US07463113B2 Apparatus and methods relating to electrically conductive path interfaces disposed within capacitor plate openings 有权
标题翻译：与设置在电容器板开口内的导电路径接口相关的装置和方法
公开(公告)号：US07463113B2
公开(公告)日：2008-12-09
申请号：US11276429
申请日：2006-02-28
申请人： Aroon Tungare , Manes Eliacin , Lih-Tyng Hwang , Robert Lempkowski , Junhua Liu , Jovica Savic
发明人： Aroon Tungare , Manes Eliacin , Lih-Tyng Hwang , Robert Lempkowski , Junhua Liu , Jovica Savic
IPC分类号： H01P1/10
CPC分类号： H01G5/16 , H01G5/011 , H01H59/0009
摘要： A first and second capacitor plate are provided (101 and 102). Each capacitor plate has an opening disposed therethrough with the second capacitor plate being disposed substantially opposite the first capacitor plate. A first electrically conductive path interface is then disposed (103) in one of these openings as is at least a second electrically conductive path interface (104).
摘要翻译：提供第一和第二电容器板（101和102）。每个电容器板具有穿过其中的开口，其中第二电容器板与第一电容器板大致相对设置。然后，至少第二导电路径接口（104）将第一导电路径界面（103）设置在这些开口之一中。

10. 发明授权

US07444727B2 Method for forming multi-layer embedded capacitors on a printed circuit board 失效
标题翻译：在印刷电路板上形成多层嵌入式电容器的方法
公开(公告)号：US07444727B2
公开(公告)日：2008-11-04
申请号：US11276688
申请日：2006-03-10
申请人： Jovica Savic , Remy J. Chelini , Gregory J. Dunn
发明人： Jovica Savic , Remy J. Chelini , Gregory J. Dunn
IPC分类号： H01G7/00 , H01L21/20
CPC分类号： H01G4/33 , H01G4/12 , H05K1/162 , H05K3/0044 , H05K2201/0175 , H05K2201/0187 , H05K2201/0195 , H05K2201/0209 , H05K2201/09509 , H05K2203/025 , Y10T29/417 , Y10T29/43 , Y10T29/435 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.
摘要翻译：公开了一种在印刷电路板上形成嵌入式电容器的方法。通过在位于PCB上的一个或多个电极上沉积第一介电层，在印刷电路板上形成电容器。另一电极形成在第一电介质层的顶部，并且第二电介质层沉积在该电极的顶部上。在第二电介质层的顶部形成第三电极。通过诸如喷砂的方法在单个步骤中擦拭两个电介质层，以限定第一和第二电介质层的部分以产生多层电容结构。

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