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1. 发明授权

US08996816B2 Method and apparatus for selectively bypassing a cache for trace collection in a processor 有权
标题翻译：用于选择性地绕过高速缓存以用于处理器中的跟踪收集的方法和装置
公开(公告)号：US08996816B2
公开(公告)日：2015-03-31
申请号：US12941576
申请日：2010-11-08
申请人： Greggory D. Donley , Benjamin Tsien , Vydhyanathan Kalyanasundharam , Patrick N. Conway , William A. Hughes
发明人： Greggory D. Donley , Benjamin Tsien , Vydhyanathan Kalyanasundharam , Patrick N. Conway , William A. Hughes
IPC分类号： G06F12/00 , G06F11/36 , G06F12/08
CPC分类号： G06F11/3636 , G06F11/3648 , G06F12/0888
摘要： A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in a trace controller buffer (TCB) for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a TCB, providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core.
摘要翻译：公开了一种用于选择性地绕过计算设备的处理器中的高速缓存的方法和装置。通过引起缓存满足的选定事务，绕过控制器缓冲区（TCB）中的高速缓存接口（例如，L3缓存接口）来提供对核心上的事务的可见性的机制，以绕过描述缓存并将其呈现给存储器系统，其中它们可以被登录在TCB中。在本发明的实施例中，提供了一种用于提供处理核心请求可见性的方法，包括响应于处理核心请求绕过较高级别的高速缓存，在TCB中捕获处理核心请求，提供掩码以过滤处理核心请求并将事务响应返回到请求处理核心。

2. 发明申请

US20120117330A1 METHOD AND APPARATUS FOR SELECTIVELY BYPASSING A CACHE FOR TRACE COLLECTION IN A PROCESSOR 有权
标题翻译：用于选择性处理加速器中追踪采集的高速缓存的方法和装置
公开(公告)号：US20120117330A1
公开(公告)日：2012-05-10
申请号：US12941576
申请日：2010-11-08
申请人： Greggory D. Donley , Benjamin Tsien , Vydhyanathan Kalyanasundharam , Patrick N. Conway , William A. Hughes
发明人： Greggory D. Donley , Benjamin Tsien , Vydhyanathan Kalyanasundharam , Patrick N. Conway , William A. Hughes
IPC分类号： G06F12/08
CPC分类号： G06F11/3636 , G06F11/3648 , G06F12/0888
摘要： A method and apparatus for a selectively bypassing a cache in a processor of a computing device are disclosed.
摘要翻译：公开了一种用于选择性地绕过计算设备的处理器中的高速缓存的方法和装置。

3. 发明申请

US20120144122A1 METHOD AND APPARATUS FOR ACCELERATED SHARED DATA MIGRATION 有权
标题翻译：用于加速共享数据迁移的方法和装置
公开(公告)号：US20120144122A1
公开(公告)日：2012-06-07
申请号：US12962156
申请日：2010-12-07
申请人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
发明人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
IPC分类号： G06F12/02 , G06F12/00 , G06F12/08
CPC分类号： G06F12/084 , G06F12/0822 , G06F12/0833 , Y02D10/13
摘要： A method and apparatus for accelerated shared data migration between cores is disclosed.
摘要翻译：公开了一种用于在核之间加速共享数据迁移的方法和装置。

4. 发明授权

US08732410B2 Method and apparatus for accelerated shared data migration 有权
标题翻译：加速共享数据迁移的方法和装置
公开(公告)号：US08732410B2
公开(公告)日：2014-05-20
申请号：US12962156
申请日：2010-12-07
申请人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
发明人： Kevin M. Lepak , Vydhyanathan Kalyanasundharam , William A. Hughes , Benjamin Tsien , Greggory D. Donley
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0822 , G06F12/0833 , Y02D10/13
摘要： A method and apparatus for accelerated shared data migration between cores. Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the entry is transitioned to an owned state, and a source done command is sent without sending cache block ownership or state information to the directory.
摘要翻译：一种用于加速内核之间共享数据迁移的方法和装置。使用始终迁移协议，当迁移探测器以修改或归属状态命中目录条目时，该条目将转换为所有状态，并且发送源完成命令，而不向缓存目录发送缓存块所有权或状态信息。

5. 发明申请

US20120159080A1 NEIGHBOR CACHE DIRECTORY 审中-公开
标题翻译：邻居缓存目录
公开(公告)号：US20120159080A1
公开(公告)日：2012-06-21
申请号：US12969343
申请日：2010-12-15
申请人： Greggory D. Donley , William A. Hughes , Kevin M. Lepak , Vydhyanathan Kalyanasundharam , Benjamin Tsien
发明人： Greggory D. Donley , William A. Hughes , Kevin M. Lepak , Vydhyanathan Kalyanasundharam , Benjamin Tsien
IPC分类号： G06F12/08
CPC分类号： G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F12/0895 , G06F2212/603
摘要： A method and apparatus for utilizing a higher-level cache as a neighbor cache directory in a multi-processor system are provided. In the method and apparatus, when the data field of a portion or all of the cache is unused, a remaining portion of the cache is repurposed for usage as neighbor cache directory. The neighbor cache provides a pointer to another cache in the multi-processor system storing memory data. The neighbor cache directory can be searched in the same manner as a data cache.
摘要翻译：提供了一种用于在多处理器系统中利用高级缓存作为相邻高速缓存目录的方法和装置。在所述方法和装置中，当高速缓存的一部分或全部的数据字段未使用时，高速缓存的剩余部分被重新利用以用作相邻高速缓存目录。邻居缓存提供指向存储存储器数据的多处理器系统中的另一高速缓存的指针。可以以与数据高速缓存相同的方式搜索邻居缓存目录。

6. 发明申请

US20120144118A1 METHOD AND APPARATUS FOR SELECTIVELY PERFORMING EXPLICIT AND IMPLICIT DATA LINE READS ON AN INDIVIDUAL SUB-CACHE BASIS 审中-公开
标题翻译：用于选择性地显示和隐藏数据行读数的方法和装置在个别子缓存基础上
公开(公告)号：US20120144118A1
公开(公告)日：2012-06-07
申请号：US12962083
申请日：2010-12-07
申请人： Benjamin Tsien , Greggory D. Donley
发明人： Benjamin Tsien , Greggory D. Donley
IPC分类号： G06F12/08
CPC分类号： G06F12/0846
摘要： A method and apparatus are described for selectively performing explicit and implicit data line reads. A controller, located in a cache, individually monitors the data resource availability for each of a plurality of sub-caches also located in the cache. The controller receives a data line request, generates an individual implicit tag request for each of the sub-caches that currently have sufficient data resources to perform an implicit data line read, and generates an individual explicit tag request for each of the sub-caches that do not currently have sufficient data resources to perform an implicit data line read. Each tag request includes an address of the requested data line and an indicator, (represented by at least one bit), of whether the tag request is an explicit or implicit tag request.
摘要翻译：描述了用于选择性地执行显式和隐式数据行读取的方法和装置。位于高速缓存中的控制器分别监视也位于高速缓存中的多个子缓存中的每一个的数据资源可用性。控制器接收数据线请求，为当前具有足够数据资源的每个子缓存生成单独的隐式标签请求，以执行隐式数据行读取，并为每个子缓存生成单独的显式标记请求，目前没有足够的数据资源来执行隐式数据行读取。每个标签请求包括所请求的数据行的地址和指示符（由至少一个比特表示）指示标签请求是否是显式或隐式标签请求。

7. 发明授权

US08595563B2 Method and circuitry for debugging a power-gated circuit 有权
标题翻译：用于调试电源门控电路的方法和电路
公开(公告)号：US08595563B2
公开(公告)日：2013-11-26
申请号：US13184982
申请日：2011-07-18
申请人： Benjamin Tsien , Kiran Bondalapati , Hao Huang , William A. Hughes , Eric Rentschler , Jeremy Schreiber , Aaron J. Grenat
发明人： Benjamin Tsien , Kiran Bondalapati , Hao Huang , William A. Hughes , Eric Rentschler , Jeremy Schreiber , Aaron J. Grenat
IPC分类号： G06F11/00
CPC分类号： G06F17/505 , G01R31/31705 , G06F2217/78
摘要： Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.
摘要翻译：描述了在电源门控序列期间分析和校正在电路工作中发生的故障的电路和方法。该方法包括执行包括维持跟踪捕获缓冲器（TCB）的操作的电源门控序列的修改; 在TCB中记录执行期间发生的事件; 并根据对TCB记录事件的分析来纠正故障。该电路包括多个包括TCB的部件和被配置为在第一状态下保持对TCB的电源并且在第二状态下关闭到TCB的电源的开关。

8. 发明申请

US20130077701A1 METHOD AND INTEGRATED CIRCUIT FOR ADJUSTING THE WIDTH OF AN INPUT/OUTPUT LINK 审中-公开
标题翻译：用于调整输入/输出链路宽度的方法和集成电路
公开(公告)号：US20130077701A1
公开(公告)日：2013-03-28
申请号：US13243086
申请日：2011-09-23
申请人： Benjamin Tsien , Kevin M. Lepak , Paul C. Miranda , William A. Hughes , Wade L. Williams , Chenping Yang , Adam L. From
发明人： Benjamin Tsien , Kevin M. Lepak , Paul C. Miranda , William A. Hughes , Wade L. Williams , Chenping Yang , Adam L. From
IPC分类号： H04L27/00
CPC分类号： G06F1/3253 , G06F13/4273 , H04L25/14 , H04W28/18 , Y02D10/151
摘要： A method and apparatus are described for adjusting a bit width of an input/output (I/O) link established between a transmitter and a receiver. The I/O link has a plurality of bit lanes. The transmitter may send to the receiver a command identifying at least one selected bit lane of the I/O link that will be powered off or powered on in response to detecting that a bit width adjustment threshold of the I/O link has been reached.
摘要翻译：描述了一种用于调整在发射机和接收机之间建立的输入/输出（I / O）链路的比特宽度的方法和装置。 I / O链路具有多个位通道。响应于检测到已经达到I / O链路的比特宽度调整阈值，发射机可以向接收机发送识别I / O链路的至少一个所选比特通道的命令，该I / O链路将被断电或上电。

9. 发明申请

US20130024829A1 METHOD AND CIRCUITRY FOR DEBUGGING A POWER-GATED CIRCUIT 有权
标题翻译：用于调试功率门控电路的方法和电路
公开(公告)号：US20130024829A1
公开(公告)日：2013-01-24
申请号：US13184982
申请日：2011-07-18
申请人： Benjamin Tsien , Kiran Bondalapati , Hao Huang , William A. Hughes , Eric Rentschler , Jeremy Schreiber , Aaron J. Grenat
发明人： Benjamin Tsien , Kiran Bondalapati , Hao Huang , William A. Hughes , Eric Rentschler , Jeremy Schreiber , Aaron J. Grenat
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31705 , G06F2217/78
摘要： Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.
摘要翻译：描述了在电源门控序列期间分析和校正在电路工作中发生的故障的电路和方法。该方法包括执行包括维持跟踪捕获缓冲器（TCB）的操作的电源门控序列的修改; 在TCB中记录执行期间发生的事件; 并根据对TCB记录事件的分析来纠正故障。该电路包括多个包括TCB的部件和被配置为在第一状态下保持对TCB的电源并且在第二状态下关闭到TCB的电源的开关。

10. 发明申请

US20120144124A1 METHOD AND APPARATUS FOR MEMORY ACCESS UNITS INTERACTION AND OPTIMIZED MEMORY SCHEDULING 审中-公开
标题翻译：用于存储器访问单元交互和优化记忆调度的方法和装置
公开(公告)号：US20120144124A1
公开(公告)日：2012-06-07
申请号：US12962042
申请日：2010-12-07
申请人： Kevin M. Lepak , Benjamin Tsien , Todd Rafacz
发明人： Kevin M. Lepak , Benjamin Tsien , Todd Rafacz
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： A method and an apparatus for modulating the prefetch training of a memory-side prefetch unit (MS-PFU) are described. An MS-PFU trains on memory access requests it receives from processors and their processor-side prefetch units (PS-PFUs). In the method and apparatus, an MS-PFU modulates its training based on one or more of a PS-PFU memory access request, a PS-PFU memory access request type, memory utilization, or the accuracy of MS-PFU prefetch requests.
摘要翻译：描述了用于调制存储器侧预取单元（MS-PFU）的预取训练的方法和装置。 MS-PFU对从处理器及其处理器端预取单元（PS-PFU）接收的存储器访问请求进行训练。在该方法和装置中，MS-PFU基于PS-PFU存储器访问请求，PS-PFU存储器访问请求类型，存储器利用率或MS-PFU预取请求的准确性中的一个或多个来调制其训练。

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