专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06998343B1 Method for creating barrier layers for copper diffusion 失效
标题翻译：用于产生铜扩散的阻挡层的方法
公开(公告)号：US06998343B1
公开(公告)日：2006-02-14
申请号：US10721971
申请日：2003-11-24
申请人： Grace Sun , Vladimir Zubkov , William K. Barth , Sethuraman Lakshminarayanan , Sey-Shing Sun , Agajan Suvkhanov , Hao Cui
发明人： Grace Sun , Vladimir Zubkov , William K. Barth , Sethuraman Lakshminarayanan , Sey-Shing Sun , Agajan Suvkhanov , Hao Cui
IPC分类号： H01L21/44
CPC分类号： H01L21/76867 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76841
摘要： A method for forming damascene interconnect copper diffusion barrier layers includes implanting calcium into the sidewalls of the trenches and vias. The calcium implantation into dielectric layers, such as oxides, is used to prevent Cu diffusion into oxide, such as during an annealing process step. The improved barrier layers of the present invention help prevent delamination of the Cu from the dielectric.
摘要翻译：用于形成镶嵌互连铜扩散阻挡层的方法包括将钙植入沟槽和通孔的侧壁中。诸如氧化物之类的介电层中的钙注入用于防止Cu扩散到氧化物中，例如在退火工艺步骤期间。本发明的改进的阻挡层有助于防止Cu从电介质分层。

2. 发明申请

US20050258475A1 Memory device having an electron trapping layer in a high-K dielectric gate stack 审中-公开
标题翻译：在高K电介质栅叠层中具有电子俘获层的存储器件
公开(公告)号：US20050258475A1
公开(公告)日：2005-11-24
申请号：US11189625
申请日：2005-07-25
申请人： Sheldon Aronowitz , Vladimir Zubkov , Grace Sun
发明人： Sheldon Aronowitz , Vladimir Zubkov , Grace Sun
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L29/78
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L29/513 , H01L29/78
摘要： An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.
摘要翻译：公开了一种改进的半导体存储器结构及其制造方法。存储器结构包括具有在半导体衬底的沟道区上形成的电介质叠层的半导体衬底。电介质堆叠包括作为存储器件的电荷存储中心工作的电子俘获材料层。栅电极与电介质叠层的顶部连接。在各种实施例中，电子捕获材料形成介电叠层的更大或更小的部分。本发明包括用于形成这种存储器件的方法实施例。

3. 发明授权

US06919263B2 High-K dielectric gate material uniquely formed 失效
标题翻译：高K介电栅极材料独特地形成
公开(公告)号：US06919263B2
公开(公告)日：2005-07-19
申请号：US10643687
申请日：2003-08-19
申请人： Sheldon Aronowitz , Vladimir Zubkov , Grace Sun
发明人： Sheldon Aronowitz , Vladimir Zubkov , Grace Sun
IPC分类号： C23C16/40 , C23C16/44 , H01L21/28 , H01L21/316 , H01L29/51 , H01L21/3205
CPC分类号： H01L29/517 , C23C16/40 , H01L21/28194 , H01L21/31604 , H01L21/31683
摘要： A new relatively high-k gate dielectric gate material comprising calcium oxide will reduce leakage from the silicon substrate to the polysilicon gate, prevent boron penetration in p-channel devices, and reduce electron trapping in the dielectric. The surface of a silicon wafer is saturated with hydroxyl groups. A calcium halide, preferably calcium bromide, is heated to a temperature sufficient to achieve atomic layer deposition, and is transported to the silicon wafer. The calcium halide reacts with the hydroxyl groups. Water is added to carry away the resultant hydrogen halide. Gaseous calcium and water are then added to form a calcium oxide gate dielectric, until the desired thickness has been achieved. In an alternative embodiment of the method, the calcium halide is transported to the silicon wafer to react with the hydroxyl groups, followed by transport of gaseous water to the silicon wafer. These two steps are repeated until the desired thickness has been achieved.
摘要翻译：包含氧化钙的新的相对高k的栅介质栅极材料将减少从硅衬底到多晶硅栅极的泄漏，防止在p沟道器件中的硼渗透，并减少电介质中的电子俘获。硅晶片的表面被羟基饱和。将卤化钙，优选溴化钙加热到足以实现原子层沉积的温度，并被输送到硅晶片。卤化钙与羟基反应。加入水以携带所得的卤化氢。然后加入气态钙和水以形成氧化钙栅极电介质，直至达到所需的厚度。在该方法的替代实施方案中，将卤化钙输送到硅晶片以与羟基反应，然后将气态水输送到硅晶片。重复这两个步骤，直到达到所需的厚度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式