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1. 发明授权

US06998343B1 Method for creating barrier layers for copper diffusion 失效
标题翻译：用于产生铜扩散的阻挡层的方法
公开(公告)号：US06998343B1
公开(公告)日：2006-02-14
申请号：US10721971
申请日：2003-11-24
申请人： Grace Sun , Vladimir Zubkov , William K. Barth , Sethuraman Lakshminarayanan , Sey-Shing Sun , Agajan Suvkhanov , Hao Cui
发明人： Grace Sun , Vladimir Zubkov , William K. Barth , Sethuraman Lakshminarayanan , Sey-Shing Sun , Agajan Suvkhanov , Hao Cui
IPC分类号： H01L21/44
CPC分类号： H01L21/76867 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76841
摘要： A method for forming damascene interconnect copper diffusion barrier layers includes implanting calcium into the sidewalls of the trenches and vias. The calcium implantation into dielectric layers, such as oxides, is used to prevent Cu diffusion into oxide, such as during an annealing process step. The improved barrier layers of the present invention help prevent delamination of the Cu from the dielectric.
摘要翻译：用于形成镶嵌互连铜扩散阻挡层的方法包括将钙植入沟槽和通孔的侧壁中。诸如氧化物之类的介电层中的钙注入用于防止Cu扩散到氧化物中，例如在退火工艺步骤期间。本发明的改进的阻挡层有助于防止Cu从电介质分层。

2. 发明授权

US06642597B1 Inter-layer interconnection structure for large electrical connections 有权
标题翻译：用于大型电气连接的层间互连结构
公开(公告)号：US06642597B1
公开(公告)日：2003-11-04
申请号：US10272767
申请日：2002-10-16
申请人： Peter A. Burke , William K. Barth
发明人： Peter A. Burke , William K. Barth
IPC分类号： H01L3100
CPC分类号： H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include an electrical interconnection structure for connection to large electrical contacts. The electrical interconnection includes a semiconductor substrate having a conductive pad layer formed thereon. A dielectric layer having a plurality of elongate trenches is formed over the conductive pad layer such that the elongate trenches extend through the dielectric layer to the underlying conductive pad layer. Elongate conductive contacts are formed in the elongate trenches to establish electrical connections to the underlying conductive pad layer. The long axes of the elongate bar trenches can be arranged substantially parallel to the long axes of the slots formed in the copper pad. Alternatively, the long axes of the bar trenches can be arranged transversely to the long axes of the slots formed in the copper pad. In some embodiments, the conductive contacts are formed such that they establish electrical connection with sidewalls of the underlying conductive pad layer. Other embodiments address the methods of manufacturing the electrical interconnection structures of the present invention.
摘要翻译：本发明的实施例包括用于连接到大电触头的电互连结构。电互连包括其上形成有导电焊盘层的半导体衬底。具有多个细长沟槽的电介质层形成在导电焊盘层上方，使得细长的沟槽延伸通过介电层延伸到下面的导电焊盘层。在细长的沟槽中形成细长的导电触点以建立与下面的导电焊盘层的电连接。细长条沟的长轴可以布置成基本上平行于形成在铜垫中的槽的长轴。或者，条形沟槽的长轴可以横向于形成在铜垫中的槽的长轴布置。在一些实施例中，导电触点形成为使得它们与下面的导电焊盘层的侧壁建立电连接。其他实施例涉及制造本发明的电互连结构的方法。

3. 发明授权

US07160805B1 Inter-layer interconnection structure for large electrical connections 有权
标题翻译：用于大型电气连接的层间互连结构
公开(公告)号：US07160805B1
公开(公告)日：2007-01-09
申请号：US10623082
申请日：2003-07-17
申请人： Peter A. Burke , William K. Barth
发明人： Peter A. Burke , William K. Barth
IPC分类号： H01L21/44
CPC分类号： H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include an electrical interconnection structure for connection to large electrical contacts. The electrical interconnection includes a semiconductor substrate having a conductive pad layer formed thereon. A dielectric layer having a plurality of elongate trenches is formed over the conductive pad layer such that the elongate trenches extend through the dielectric layer to the underlying conductive pad layer. Elongate conductive contacts are formed in the elongate trenches to establish electrical connections to the underlying conductive pad layer. The long axes of the elongate bar trenches can be arranged substantially parallel to the long axes of the slots formed in the copper pad. Alternatively, the long axes of the bar trenches can be arranged transversely to the long axes of the slots formed in the copper pad. In some embodiments, the conductive contacts are formed such that they establish electrical connection with sidewalls of the underlying conductive pad layer. Other embodiments address the methods of manufacturing the electrical interconnection structures of the present invention.
摘要翻译：本发明的实施例包括用于连接到大电触头的电互连结构。电互连包括其上形成有导电焊盘层的半导体衬底。具有多个细长沟槽的电介质层形成在导电焊盘层上方，使得细长的沟槽延伸通过介电层延伸到下面的导电焊盘层。在细长的沟槽中形成细长的导电触点以建立与下面的导电焊盘层的电连接。细长条沟的长轴可以布置成基本上平行于形成在铜垫中的槽的长轴。或者，条形沟槽的长轴可以横向于形成在铜垫中的槽的长轴布置。在一些实施例中，导电触点形成为使得它们与下面的导电焊盘层的侧壁建立电连接。其他实施例涉及制造本发明的电互连结构的方法。

4. 发明授权

US07312532B2 Dual damascene interconnect structure with improved electro migration lifetimes 有权
标题翻译：双镶嵌互连结构，具有改善的电迁移寿命
公开(公告)号：US07312532B2
公开(公告)日：2007-12-25
申请号：US11090107
申请日：2005-03-24
申请人： Peter A. Burke , William K. Barth , Hongqiang Lu
发明人： Peter A. Burke , William K. Barth , Hongqiang Lu
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L21/76808 , H01L21/76813 , H01L21/76838 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.
摘要翻译：通过图案化第一电介质以形成金属线来形成双镶嵌互连结构。第二电介质设置在第一电介质上并被图案化以形成通孔。第一金属线以相对于通孔接合的结构进行图案化，使得当将进入第二电介质的通孔蚀刻延伸到第一电介质中时形成空腔。在形成通孔的情况下，以一体的方式填充导电金属以形成通孔突起，以改善通孔和金属线之间的电接触。

5. 发明授权

US07033929B1 Dual damascene interconnect structure with improved electro migration lifetimes 失效
标题翻译：双镶嵌互连结构，具有改善的电迁移寿命
公开(公告)号：US07033929B1
公开(公告)日：2006-04-25
申请号：US10328333
申请日：2002-12-23
申请人： Peter A. Burke , William K. Barth , Hongqiang Lu
发明人： Peter A. Burke , William K. Barth , Hongqiang Lu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813 , H01L21/76838 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.
摘要翻译：通过图案化第一电介质以形成金属线来形成双镶嵌互连结构。第二电介质设置在第一电介质上并被图案化以形成通孔。第一金属线以相对于通孔接合的结构进行图案化，使得当将进入第二电介质的通孔蚀刻延伸到第一电介质中时形成空腔。在形成通孔的情况下，以一体的方式填充导电金属以形成通孔突起，以改善通孔和金属线之间的电接触。

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