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1. 发明授权

US5136714A Method and apparatus for implementing inter-processor interrupts using shared memory storage in a multi-processor computer system 失效
标题翻译：在多处理器计算机系统中使用共享存储器存储来实现处理器间中断的方法和装置
公开(公告)号：US5136714A
公开(公告)日：1992-08-04
申请号：US445202
申请日：1989-12-04
申请人： Gordon W. Braudaway , Ben J. Nathanson
发明人： Gordon W. Braudaway , Ben J. Nathanson
IPC分类号： G06F15/16 , G06F9/46 , G06F15/167 , G06F15/177
CPC分类号： G06F15/167
摘要： An inter-processor interrupt mechanism is implemented in a shared-memory multi-processor system. A dedicated halfword for each processor in said multi-processor system is provided in the shared memory restricted in use to the generation and control of inter-processor interrupts. No data in any dedicated shared-memory location can be altered by any processor unless it has "captured" the location by executing a test and set halfword instruction and a captured shared-memory location being released only by executing a store halfword instruction. An address comparator and a zero detector are added as adjunct operations to read-modify-write logic of each processor's memory interface. When any instruction is executed and its operand address agrees with that contained in the address comparator, an inter-processor interrupt request is generated if zero is not detected on all predefined data bits being written to memory. If a zero is detected on all predefined data bits being written to memory, the inter-processor interrupt request is removed.

2. 发明授权

US5664223A System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively 失效
标题翻译：使用分别耦合在FIFO缓冲器和两个独立总线之间的两个独立控制的DMA引擎来独立传输数据的系统
公开(公告)号：US5664223A
公开(公告)日：1997-09-02
申请号：US223144
申请日：1994-04-05
申请人： Carl A. Bender , Gerard M. Salem , Richard A. Swetz , Singpui Zee , Ben J. Nathanson
发明人： Carl A. Bender , Gerard M. Salem , Richard A. Swetz , Singpui Zee , Ben J. Nathanson
IPC分类号： G06F13/36 , G06F1/04 , G06F13/28 , G06F3/00
CPC分类号： G06F13/28
摘要： An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance with the communication protocol, and wherein the first and second DMA engines transfer data for the packets independently of each other.
摘要翻译：一种用于在主处理器及其存储器之间传送数据和分组交换机的装置包括耦合到主处理器及其存储器的第一总线，耦合在第一总线和第二总线之间的双向先进先出（FIFO）缓冲器总线，并且具有连接到第一总线的第一端口和连接到第二总线的第二端口，耦合到第二总线的通信处理器，可操作地耦合到第二总线的存储器，第一直接存储器访问（DMA）引擎耦合在第一总线和FIFO缓冲器之间，用于在主处理器和FIFO缓冲器之间传送数据;耦合在FIFO缓冲器和第二总线之间的第二直接存储器访问（DMA）引擎，用于在FIFO缓冲器和第二总线之间传送数据以及可操作地耦合在第二总线和开关之间的分组交换接口，用于将第二总线与交换机接口，其中分组在主处理器的存储器和根据通信协议切换，并且其中第一和第二DMA引擎相互独立地传送数据包的数据。

3. 发明授权

US07817585B2 Data capture technique for high speed signaling 有权
标题翻译：高速信号数据采集技术
公开(公告)号：US07817585B2
公开(公告)日：2010-10-19
申请号：US12191893
申请日：2008-08-14
申请人： Wayne M. Barrett , Dong Chen , Paul W. Coteus , Alan G. Gara , Rory Jackson , Gerard V. Kopcsay , Ben J. Nathanson , Pavlos M. Vranas
发明人： Wayne M. Barrett , Dong Chen , Paul W. Coteus , Alan G. Gara , Rory Jackson , Gerard V. Kopcsay , Ben J. Nathanson , Pavlos M. Vranas
IPC分类号： H04L5/14
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.
摘要翻译：用于高速信令的数据捕获技术，以允许异步数据流的最佳采样。这种技术允许极高的数据速率，并且不要求在源同步系统中进行数据发送时钟。本发明还提供了用于自动调整用于最佳两比特双向（SiBiDi）信令的传输延迟的硬件机制。

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