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1. 发明授权

US06778002B2 Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit 有权
标题翻译：包括衬底偏置控制器和限流电路的半导体集成电路器件
公开(公告)号：US06778002B2
公开(公告)日：2004-08-17
申请号：US10207903
申请日：2002-07-31
申请人： Masayuki Miyazaki , Koichiro Ishibashi , Goichi Ono
发明人： Masayuki Miyazaki , Koichiro Ishibashi , Goichi Ono
IPC分类号： H03K301
CPC分类号： G05F3/205
摘要： In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.
摘要翻译：在半导体集成电路装置中，为了实现高速化以及优异的产品成品率和可用性，在减小电路规模并提高产品产率和可靠性的同时，将由CMOS元件构成的主电路耦合到速度用于形成对应于其工作速度的速度信号的监视器电路和用于响应速度监视电路向主电路提供相应衬底偏置电压的衬底偏置控制器。还结合衬底偏置控制器提供限流电路，以防止由于偏置电压引起的电流溢出。

2. 发明授权

US06833750B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06833750B2
公开(公告)日：2004-12-21
申请号：US10321616
申请日：2002-12-18
申请人： Masayuki Miyazaki , Goichi Ono , Koichiro Ishibashi
发明人： Masayuki Miyazaki , Goichi Ono , Koichiro Ishibashi
IPC分类号： G05F110
CPC分类号： G11C5/143 , G11C5/146
摘要： A semiconductor integrated circuit and power control method use one of a supply voltage of the circuit and a delay time of the circuit to control a substrate bias voltage applied to a substrate of an insulated gate field effect transistor. High speed operation, consuming a small amount of power, is achieved. A CMOS circuit has a widened operating voltage range, with reduced leak currents in a standby mode in a range of high supply voltage, reducing power consumption of the CMOS circuit, and increasing operating speed of the CMOS circuit in the range of low supply voltage.
摘要翻译：半导体集成电路和功率控制方法使用电路的电源电压和电路的延迟时间之一来控制施加到绝缘栅场效应晶体管的衬底的衬底偏置电压。实现高速运转，消耗少量电力。 CMOS电路具有加宽的工作电压范围，在待机模式下在高电源电压范围内减小泄漏电流，降低CMOS电路的功耗，以及在低电源电压范围内提高CMOS电路的工作速度。

3. 发明授权

US06653890B2 Well bias control circuit 失效
标题翻译：良好的偏置控制电路
公开(公告)号：US06653890B2
公开(公告)日：2003-11-25
申请号：US10284207
申请日：2002-10-31
申请人： Goichi Ono , Masayuki Miyazaki , Koichiro Ishibashi
发明人： Goichi Ono , Masayuki Miyazaki , Koichiro Ishibashi
IPC分类号： G05F146
CPC分类号： H03K19/00384 , H03K2217/0018
摘要： Disclosed is a semiconductor integrated circuit device having a control mechanism 11 for compensating not only circuit operational speed but also variations in leakage current, which includes: a main circuit 10 constructed by a CMOS; a delay monitor 21 for simulating a critical path of the main circuit 10 constructed by a CMOS and monitoring a delay of the path; a PN Vt balance compensation circuit 23 for detecting a threshold voltage difference between a PMOS transistor and an NMOS transistor; and a well bias generating circuit 25 for receiving outputs of the delay monitor 21 and the PN Vt balance compensation circuit 23 and applying a well bias to the delay monitor 21 and the main circuit 10 so as to compensate the operation speed of the delay monitor 21 to a desired speed and reduce a threshold voltage difference between the PMOS and NMOS transistors.
摘要翻译：公开了一种半导体集成电路器件，具有控制机构11，用于不仅补偿电路工作速度，而且补偿漏电流的变化，其中包括：由CMOS构成的主电路10; 延迟监视器21，用于模拟由CMOS构成的主电路10的关键路径并监视路径的延迟; 用于检测PMOS晶体管和NMOS晶体管之间的阈值电压差的PN Vt平衡补偿电路23; 以及用于接收延迟监视器21和PN Vt平衡补偿电路23的输出并向延迟监视器21和主电路10施加阱偏压的阱偏置产生电路25，以补偿延迟监视器21的操作速度达到期望的速度并且降低PMOS和NMOS晶体管之间的阈值电压差。

4. 发明授权

US06847252B1 Semiconductor integrated circuit device 失效
标题翻译：良好的偏压控制电路及方法
公开(公告)号：US06847252B1
公开(公告)日：2005-01-25
申请号：US10671477
申请日：2003-09-29
申请人： Goichi Ono , Masayuki Miyazaki , Koichiro Ishibashi
发明人： Goichi Ono , Masayuki Miyazaki , Koichiro Ishibashi
IPC分类号： H01L21/822 , G11C11/40 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K17/30 , H03K19/003 , G05F1/46
CPC分类号： H03K19/00384 , H03K2217/0018
摘要： A semiconductor integrated circuit device having a mechanism of compensating not only circuit operational speed but also variations in leakage current, which includes: a main circuit constructed with CMOS device, a delay monitor for simulating a critical path of the main circuit constructed by a CMOS and monitoring a delay of the path, a PN Vt balance compensation circuit for detecting a threshold voltage difference between a PMOS transistor and an NMOS transistor, and a well bias generating circuit for receiving outputs of the delay monitor and the PN Vt balance compensation circuit and applying a well bias to the delay monitor and the main circuit so as to compensate the operation speed of the delay monitor to a desired speed and reduce a threshold voltage difference between the PMOS and NMOS transistors.
摘要翻译：一种半导体集成电路器件，其具有不仅补偿电路工作速度而且补偿漏电流的变化的机构，其包括：由CMOS器件构成的主电路，用于模拟由CMOS构成的主电路的关键路径的延迟监视器，以及监视路径的延迟，用于检测PMOS晶体管和NMOS晶体管之间的阈值电压差的PN Vt平衡补偿电路，以及用于接收延迟监视器和PN Vt平衡补偿电路的输出的阱偏压产生电路，以及应用延迟监视器和主电路的良好偏置，以便将延迟监视器的操作速度补偿到期望的速度并且减小PMOS和NMOS晶体管之间的阈值电压差。

5. 发明授权

US06867637B2 Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit 有权
标题翻译：包括衬底偏置控制器和限流电路的半导体集成电路器件
公开(公告)号：US06867637B2
公开(公告)日：2005-03-15
申请号：US10889141
申请日：2004-07-13
申请人： Masayuki Miyazaki , Koichiro Ishibashi , Goichi Ono
发明人： Masayuki Miyazaki , Koichiro Ishibashi , Goichi Ono
IPC分类号： H01L27/04 , G05F3/20 , G11C11/34 , G11C11/408 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K5/135 , H03K19/094 , H03M1/66 , H03K3/01
CPC分类号： G05F3/205
摘要： In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.
摘要翻译：在半导体集成电路装置中，为了实现高速化以及优异的产品成品率和可用性，在减小电路规模并提高产品产率和可靠性的同时，将由CMOS元件构成的主电路耦合到速度用于形成对应于其工作速度的速度信号的监视器电路和用于响应速度监视电路向主电路提供相应衬底偏置电压的衬底偏置控制器。还结合衬底偏置控制器提供限流电路，以防止由于偏置电压引起的电流溢出。

6. 发明授权

US06518825B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06518825B2
公开(公告)日：2003-02-11
申请号：US09863349
申请日：2001-05-24
申请人： Masayuki Miyazaki , Goichi Ono , Koichiro Ishibashi
发明人： Masayuki Miyazaki , Goichi Ono , Koichiro Ishibashi
IPC分类号： H03K301
CPC分类号： G11C5/143 , G11C5/146
摘要： In a semiconductor integrated circuit device comprising a CMOS circuit, the CMOS circuit operating at a high speed, consuming a small amount of power, is achieved. In particular, acceleration of the operating speed under low voltage is achieved. The semiconductor integrated circuit device of the invention comprises a main circuit including a CMOS circuit, a changeover circuit, a substrate bias control circuit and a switching circuit and, in accordance with a changing signal from the changeover circuit, switches states of a substrate of a MOS transistor of the main circuit between a state in which normal supply voltage as well as ground voltage are applied and a state in which forward bias is applied. The changeover circuit detects a drop in supply voltage, etc. and outputs changing signals.
摘要翻译：在包括CMOS电路的半导体集成电路器件中，实现高速运行的CMOS电路，消耗少量的功率。特别地，实现了低电压下的运行速度的加速。本发明的半导体集成电路器件包括：主电路，包括CMOS电路，转换电路，衬底偏置控制电路和开关电路，并且根据来自转换电路的变化信号，切换基片的状态在施加正常供电电压和接地电压的状态之间的主电路的MOS晶体管和施加正向偏压的状态。切换电路检测电源电压等的下降，并输出变化的信号。

7. 发明授权

US06466077B1 Semiconductor integrated circuit device including a speed monitor circuit and a substrate bias controller responsive to the speed-monitor circuit 有权
标题翻译：半导体集成电路装置包括速度监视器电路和响应速度监视器电路的衬底偏置控制器
公开(公告)号：US06466077B1
公开(公告)日：2002-10-15
申请号：US09661371
申请日：2000-09-13
申请人： Masayuki Miyazaki , Koichiro Ishibashi , Goichi Ono
发明人： Masayuki Miyazaki , Koichiro Ishibashi , Goichi Ono
IPC分类号： H03K301
CPC分类号： G05F3/205
摘要： In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit.
摘要翻译：在半导体集成电路装置中，为了实现高速化以及优异的产品成品率和可用性，在减小电路规模并提高产品产率和可靠性的同时，将由CMOS元件构成的主电路耦合到速度用于形成对应于其工作速度的速度信号的监视器电路和用于响应速度监视电路向主电路提供相应衬底偏置电压的衬底偏置控制器。

8. 发明申请

US20080116934A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20080116934A1
公开(公告)日：2008-05-22
申请号：US11970370
申请日：2008-01-07
申请人： Hiroyuki Mizuno , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and generating a first substrate bias voltage in response thereto, the first substrate bias voltage being supplied to substrates of the PMOS transistors in the oscillation circuit, and a second substrate bias generator including a second phase/frequency compare circuit that compares the output signal from the frequency-variable oscillation circuit with the reference clock and generating a second substrate bias voltage in response thereto, the second substrate bias voltage being supplied to substrates of the NMOS transistors in the oscillation circuit.
摘要翻译：一种半导体器件，包括具有多个反相器的频率可变振荡电路，每个反相器具有PMOS晶体管和NMOS晶体管，第一衬底偏置发生器包括第一相位/频率比较电路，其比较来自频率变量具有参考时钟信号的振荡电路，并响应于此产生第一衬底偏置电压，第一衬底偏置电压被提供给振荡电路中的PMOS晶体管的衬底，第二衬底偏置发生器包括第二相/频率比较电路其将来自频率可变振荡电路的输出信号与参考时钟进行比较，并响应于此产生第二衬底偏置电压，第二衬底偏置电压被提供给振荡电路中的NMOS晶体管的衬底。

9. 发明申请

US20070063735A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070063735A1
公开(公告)日：2007-03-22
申请号：US11526612
申请日：2006-09-26
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H03K19/0175
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.
摘要翻译：一种半导体集成电路器件，包括在半导体衬底上包含MIS晶体管的逻辑电路，用于控制逻辑电路中的MIS晶体管的阈值电压的控制电路，在半导体衬底上包含MIS晶体管的振荡电路，以及缓冲电路，控制电路比较振荡输出的频率和时钟信号的频率，输出第一控制信号，第一控制信号控制振荡电路的MIS晶体管的阈值电压，缓冲电路输入所述第一控制信号输出对应于所述第一控制信号的第二控制信号，所述第二控制信号控制所述逻辑电路的所述MIS晶体管的阈值电压。

10. 发明授权

US07112999B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07112999B2
公开(公告)日：2006-09-26
申请号：US11124060
申请日：2005-05-09
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.

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