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1. 发明授权

US07023041B2 Trench capacitor vertical structure 有权
标题翻译：沟槽电容器垂直结构
公开(公告)号：US07023041B2
公开(公告)日：2006-04-04
申请号：US10341187
申请日：2003-01-13
申请人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
发明人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/945 , H01L27/10861 , H01L27/10894 , H01L29/66181
摘要： A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.
摘要翻译：基于深沟槽垂直晶体管DRAM单元形成通用结构，其在与垂直晶体管的下电极接触的细长沟槽中形成沟槽电极的导电延伸。该结构可以用作电容器，作为单晶体管放大器的分立晶体管或作为更复杂电路的构建块。

2. 发明授权

US07485520B2 Method of manufacturing a body-contacted finfet 有权
标题翻译：制造身体接触鳍片的方法
公开(公告)号：US07485520B2
公开(公告)日：2009-02-03
申请号：US11773607
申请日：2007-07-05
申请人： Huilong Zhu , Thomas W. Dyer , Jack A. Mandelman , Werner Rausch
发明人： Huilong Zhu , Thomas W. Dyer , Jack A. Mandelman , Werner Rausch
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L29/66795 , H01L29/785
摘要： A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin.
摘要翻译：在半导体衬底上形成含硅翅片。在含硅翅片的底部周围形成氧化硅层。在含硅鳍上形成栅电介质，形成栅电极。在保护半导体翅片周围的通道的部分的同时，通过各向同性的蚀刻蚀刻含硅半导体鳍片的底部部分，从而在含硅鳍片上的finFET的通道和硅下方的下面的半导体层之间留下体带氧化层。翅片可以包括不均匀层的堆叠，其中底层被选择性地蚀刻到顶部半导体层。或者，翅片可以包括均匀的半导体材料，并且含硅翅片可以由含硅翅片的侧壁和顶表面上的电介质膜保护。

3. 发明申请

US20080121994A1 DEEP JUNCTION SOI MOSFET WITH ENHANCED EDGE BODY CONTACTS 失效
标题翻译：具有增强边缘接触体的DEEP JUNCTION SOI MOSFET
公开(公告)号：US20080121994A1
公开(公告)日：2008-05-29
申请号：US11564352
申请日：2006-11-29
申请人： Thomas W. Dyer , Zhijiong Luo , Jack A. Mandelman
发明人： Thomas W. Dyer , Zhijiong Luo , Jack A. Mandelman
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78615 , H01L29/66772 , H01L29/78603 , H01L29/78618
摘要： A semiconductor structure is provided that has body contacts that are located at the edges of the device channel and a buried insulating region under the device channel that is shallower than the buried insulating regions under the source/drain junctions. A method of forming such a semiconductor structure is also described. The inventive method provides for self-alignment of the various features mentioned above with the gate conductor of the structure.
摘要翻译：提供半导体结构，其具有位于器件沟道的边缘处的体接触以及在器件沟道下方比在源极/漏极结下方的掩埋绝缘区域浅的掩埋绝缘区域。还描述了形成这种半导体结构的方法。本发明的方法提供了上述各种特征与结构的栅极导体的自对准。

4. 发明申请

US20090008705A1 BODY-CONTACTED FINFET 有权
标题翻译：身体接触式FINFET
公开(公告)号：US20090008705A1
公开(公告)日：2009-01-08
申请号：US11773607
申请日：2007-07-05
申请人： Huilong Zhu , Thomas W. Dyer , Jack A. Mandelman , Werner Rausch
发明人： Huilong Zhu , Thomas W. Dyer , Jack A. Mandelman , Werner Rausch
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7842 , H01L29/66795 , H01L29/785
摘要： A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin.
摘要翻译：在半导体衬底上形成含硅翅片。在含硅翅片的底部周围形成氧化硅层。在含硅鳍上形成栅电介质，形成栅电极。在保护半导体翅片周围的通道的部分的同时，通过各向同性的蚀刻蚀刻含硅半导体鳍片的底部部分，从而在含硅鳍片上的finFET的通道和硅下方的下面的半导体层之间留下体带氧化层。翅片可以包括不均匀层的堆叠，其中底层被选择性地蚀刻到顶部半导体层。或者，翅片可以包括均匀的半导体材料，并且含硅翅片可以由含硅翅片的侧壁和顶表面上的电介质膜保护。

5. 发明授权

US06897107B2 Method for forming TTO nitride liner for improved collar protection and TTO reliability 失效
标题翻译：用于形成TTO氮化物衬垫以改善套环保护和TTO可靠性的方法
公开(公告)号：US06897107B2
公开(公告)日：2005-05-24
申请号：US10720490
申请日：2003-11-24
申请人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachajam C. Jaiprakash
发明人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachajam C. Jaiprakash
IPC分类号： H01L21/316 , H01L21/318 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10864 , H01L21/31612 , H01L21/3185 , H01L27/10867
摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.
摘要翻译：在垂直MOSFET DRAM单元器件形成期间，能够在沟槽顶氧化物TTO（高密度等离子体）HDP沉积之前沉积薄氮化物衬垫的结构和方法。随后在TTO侧壁蚀刻之后移除该衬垫。该衬垫的一个功能是在TTO氧化物侧壁蚀刻期间保护套环氧化物不被蚀刻，并且通常提供在当前处理方案中未实现的横向蚀刻保护。工艺顺序不依赖于以前沉积的膜用于套环保护，并且将TTO侧壁蚀刻保护与先前的处理步骤解耦以提供附加的工艺灵活性，例如在节点氮化物去除期间允许更薄的带切割掩模氮化物和更大的氮化物蚀刻和掩埋带氮化界面去除。有利地，在TTO之下的氮化物衬垫的存在降低了垂直MOSFET DRAM单元的栅极和电容器节点电极之间的TTO介质击穿的可能性，同时确保带扩散到栅极导体重叠。

6. 发明授权

US07550330B2 Deep junction SOI MOSFET with enhanced edge body contacts 失效
标题翻译：具有增强的边缘体接触的深结SOI MOSFET
公开(公告)号：US07550330B2
公开(公告)日：2009-06-23
申请号：US11564352
申请日：2006-11-29
申请人： Thomas W. Dyer , Zhijiong Luo , Jack A. Mandelman
发明人： Thomas W. Dyer , Zhijiong Luo , Jack A. Mandelman
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/78615 , H01L29/66772 , H01L29/78603 , H01L29/78618
摘要： A semiconductor structure is provided that has body contacts that are located at the edges of the device channel and a buried insulating region under the device channel that is shallower than the buried insulating regions under the source/drain junctions. A method of forming such a semiconductor structure is also described. The inventive method provides for self-alignment of the various features mentioned above with the gate conductor of the structure.
摘要翻译：提供半导体结构，其具有位于器件沟道的边缘处的体接触以及在器件沟道下方比在源极/漏极结下方的掩埋绝缘区域浅的掩埋绝缘区域。还描述了形成这种半导体结构的方法。本发明的方法提供了上述各种特征与结构的栅极导体的自对准。

7. 发明申请

US20080169535A1 SUB-LITHOGRAPHIC FACETING FOR MOSFET PERFORMANCE ENHANCEMENT 审中-公开
标题翻译：用于MOSFET性能增强的次平面成像
公开(公告)号：US20080169535A1
公开(公告)日：2008-07-17
申请号：US11622588
申请日：2007-01-12
申请人： Shahid A. Butt , Thomas W. Dyer , Oh-Jung Kwon , Jack A. Mandelman , Haining S. Yang
发明人： Shahid A. Butt , Thomas W. Dyer , Oh-Jung Kwon , Jack A. Mandelman , Haining S. Yang
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/3086 , H01L21/28123 , H01L21/3088 , H01L21/823807 , H01L29/0673 , H01L29/1037 , H01L29/78
摘要： The present invention provides structures and methods for providing multiple parallel V-shaped faceted grooves with sub-lithographic widths on a semiconductor substrate for enhanced performance MOSFETs. A self-aligning self-assembling material is used to pattern multiple parallel sub-lithographic lines. By employing an anisotropic etch that produces crystallographic facets on a semiconductor surface, multiple adjoining parallel V-shaped grooves with sub-lithographic groove widths are formed. While providing enhanced mobility for the MOSFET, the width of the MOSFET is not limited by the depth of focus in subsequent lithographic steps or the thickness of semiconductor layer above a BOX layer due to the sub-lithographic widths of the V-shaped grooves and the consequent reduction in the variation of the vertical profile. Also, the MOSFET has a well defined threshold voltage due to the narrow widths of each facet.
摘要翻译：本发明提供了用于在半导体衬底上提供具有亚光刻宽度的多个平行V形刻面槽以提高性能MOSFET的结构和方法。使用自对准自组装材料来对多个平行的次平版印刷线进行图案化。通过采用在半导体表面上产生结晶小面的各向异性蚀刻，形成具有亚光刻槽宽度的多个相邻的平行V形槽。在为MOSFET提供增强的移动性的同时，MOSFET的宽度不受后续光刻步骤中的深度深度或BOX层上方的半导体层厚度的限制，这是由于V形沟槽的次平版印刷宽度和从而导致垂直剖面变化的减小。此外，由于每个刻面的窄宽度，MOSFET具有明确的阈值电压。

8. 发明授权

US06809368B2 TTO nitride liner for improved collar protection and TTO reliability 失效
公开(公告)号：US06809368B2
公开(公告)日：2004-10-26
申请号：US09832605
申请日：2001-04-11
申请人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachalam C. Jaiprakash
发明人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachalam C. Jaiprakash
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L21/31612 , H01L21/3185 , H01L27/10867
摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

9. 发明授权

US06518616B2 Vertical gate top engineering for improved GC and CB process windows 有权
公开(公告)号：US06518616B2
公开(公告)日：2003-02-11
申请号：US09837799
申请日：2001-04-18
申请人： Thomas W. Dyer , Stephan P. Kudelka , Venkatachaiam C. Jaiprakash , Carl J. Radens
发明人： Thomas W. Dyer , Stephan P. Kudelka , Venkatachaiam C. Jaiprakash , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10888
摘要： A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

10. 发明申请

US20130001660A1 PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 失效
公开(公告)号：US20130001660A1
公开(公告)日：2013-01-03
申请号：US13615955
申请日：2012-09-14
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/30608 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/7848
摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

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