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1. 发明申请

US20180089007A1 DETECTING ROOT CAUSES OF USE-AFTER-FREE MEMORY ERRORS 审中-公开
公开(公告)号：US20180089007A1
公开(公告)日：2018-03-29
申请号：US15274481
申请日：2016-09-23
申请人： Justin E. Gottschlich , Gilles A. Pokam , Cristiano L. Pereira , Michael F. Spear
发明人： Justin E. Gottschlich , Gilles A. Pokam , Cristiano L. Pereira , Michael F. Spear
IPC分类号： G06F11/07 , G06F11/30
CPC分类号： G06F11/3051 , G06F11/073 , G06F11/0775 , G06F11/079 , G06F11/3034
摘要： Methods, systems, and computer programs are presented for detecting the root cause in use-after-free (UAF) memory corruption errors. A method includes an operation for tracking access to memory by a program to detect access to memory not allocated by the program. The method further includes operations for tracking allocations and deallocations of memory by the program, and for storing, in response to detecting a deallocation of memory by the program, at least part of a state of a program stack at a time of the deallocation of memory. Further, the method includes an operation for detecting, after the deallocation, access by the program to the memory associated with the deallocation of memory. In response to the detecting, the state of the program stack is saved in permanent storage at the time of the deallocation.

2. 发明申请

US20160283302A1 TECHNOLOGIES FOR ROOT CAUSE IDENTIFICATION OF USE-AFTER-FREE MEMORY CORRUPTION BUGS 有权
标题翻译：技术因素导致无使用内存损坏BUG的识别
公开(公告)号：US20160283302A1
公开(公告)日：2016-09-29
申请号：US14670863
申请日：2015-03-27
申请人： Justin E. Gottschlich , Gilles A. Pokam , Cristiano L. Pereira
发明人： Justin E. Gottschlich , Gilles A. Pokam , Cristiano L. Pereira
IPC分类号： G06F11/07
CPC分类号： G06F11/079 , G06F11/073
摘要： Technologies for identification of a potential root cause of a use-after-free memory corruption bug of a program include a computing device to replay execution of the execution of the program based on an execution log of the program. The execution log comprises an ordered set of executed instructions of the program that resulted in the use-after-free memory corruption bug. The computing device compares a use-after-free memory address access of the program to a memory address associated with an occurrence of the use-after-free memory corruption bug in response to detecting the use-after-free memory address access and records the use-after-free memory address access of the program as a candidate for a root cause of the use-after-free memory corruption bug to a candidate list in response to detecting a match between the use-after-free memory address access of the program and the memory address associated with the occurrence of the use-after-free memory corruption bug.
摘要翻译：用于识别程序的无使用存储器内存损坏错误的潜在根本原因的技术包括基于程序的执行日志来重放执行程序的计算设备。执行日志包括导致使用随机存储器损坏错误的程序的执行指令的有序集合。计算装置响应于检测到使用无存储器存储器地址访问而将程序的无用空闲存储器地址访问与与使用无释放存储器损坏错误的发生相关联的存储器地址进行比较，并且记录响应于检测到所述无用存储器内存地址访问之间的匹配，将所述程序的无用空闲内存地址访问作为候选列表的候选者，作为所述无用存储器内存损坏错误的根本原因程序和与使用随机存储器内存损坏错误的发生相关联的存储器地址。

3. 发明申请

US20140089642A1 METHODS AND SYSTEMS FOR PERFORMING A REPLAY EXECUTION 有权
标题翻译：执行重复执行的方法和系统
公开(公告)号：US20140089642A1
公开(公告)日：2014-03-27
申请号：US13629131
申请日：2012-09-27
申请人： Justin E. Gottschlich , Klaus Danne , Cristiano L. Pereira , Gilles A. Pokam , Rolf Kassa , Shiliang Hu , Tim Kranich
发明人： Justin E. Gottschlich , Klaus Danne , Cristiano L. Pereira , Gilles A. Pokam , Rolf Kassa , Shiliang Hu , Tim Kranich
IPC分类号： G06F9/30
CPC分类号： G06F9/3005 , G06F9/30072 , G06F9/3802 , G06F9/3851 , G06F9/44 , G06F9/455 , G06F9/52 , G06F11/30 , G06F11/3414 , G06F11/3476 , G06F11/36 , G06F11/3664 , G06F11/3688 , G06F2201/815 , G06F2201/825 , G06F2201/865
摘要： One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.
摘要翻译：一个或多个实施例可以提供用于执行重放的方法。该方法包括启动程序的执行，程序具有多组指令，并且每组指令具有多个指令块。该方法还包括通过在处理器上执行的虚拟机单元截取在执行之前块数量的指令。该方法还包括通过在处理器上执行的重播模块确定该块是否是活动块，并且响应于该块作为活动块来执行该指令。

4. 发明申请

US20150120996A1 TRACING MECHANISM FOR RECORDING SHARED MEMORY INTERLEAVINGS ON MULTI-CORE PROCESSORS 有权
标题翻译：用于记录多核处理器的共享存储器间隔的跟踪机制
公开(公告)号：US20150120996A1
公开(公告)日：2015-04-30
申请号：US13997747
申请日：2012-03-30
申请人： Gilles A. Pokam , Cristiano L. Pereira
发明人： Gilles A. Pokam , Cristiano L. Pereira , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/08 , G06F12/02 , G06F13/16 , G11C7/10
CPC分类号： G06F12/0815 , G06F9/30043 , G06F11/3636 , G06F12/023 , G06F13/1663 , G06F2212/622 , G11C7/1072 , Y02D10/14
摘要： A memory race recorder (MRR) is provided. The MRR includes a multi-core processor having a relaxed memory consistency model, an extension to the multi-core processor, the extension to store chunks, the chunk having a chunk size (CS) and an instruction count (IC), and a plurality of cores to execute instructions. The plurality of cores executes load/store instructions to/from a store buffer (STB) and a simulated memory to store the value when the value is not in the STB. The oldest value in the STB is transferred to the simulated memory when the IC is equal to zero and the CS is greater than zero. The MRR logs a trace entry comprising the CS, the IC, and a global timestamp, the global timestamp proving a total order across all logged chunks.
摘要翻译：提供了一个记忆体记录仪（MRR）。 MRR包括具有放松的存储器一致性模型的多核处理器，多核处理器的扩展，存储块的扩展，具有块大小（CS）和指令计数（IC）的块，以及多个的核心执行指令。多个核对存储缓冲器（STB）和模拟存储器执行加载/存储指令以在值不在STB中时存储该值。当IC等于零并且CS大于零时，STB中的最旧值被传送到模拟存储器。 MRR记录包含CS，IC和全局时间戳的跟踪条目，全局时间戳记证明所有记录的块的总顺序。

5. 发明申请

US20140366006A1 VISUALIZING RECORDED EXECUTIONS OF MULTI-THREADED SOFTWARE PROGRAMS FOR PERFORMANCE AND CORRECTNESS 审中-公开
标题翻译：可视化多线程软件程序的性能和正确性的记录执行
公开(公告)号：US20140366006A1
公开(公告)日：2014-12-11
申请号：US13997786
申请日：2013-03-13
申请人： Justin E. Gottschlich , Gilles A. Pokam , Cristiano L. Pereira , Klaus Danne , Shiliang Hu , Rolf Kassa
发明人： Justin E. Gottschlich , Gilles A. Pokam , Cristiano L. Pereira , Klaus Danne , Shiliang Hu , Rolf Kassa
IPC分类号： G06F11/36 , G06T13/80
CPC分类号： G06F11/3664 , G06F9/38 , G06F11/323 , G06F11/3404 , G06F2201/865 , G06T11/206 , G06T13/80
摘要： A system graphically visualizes performance and/or correctness features of a recorded execution of a multi-threaded software program. The system may process chunk-based information recorded during an execution of the multi-threaded program, prepare a graphical visualization of the recorded information, and display the graphical visualization on a display in an animated fashion. The system may allow a viewer to interactively control the display of the animated graphical visualization.
摘要翻译：系统以图形方式可视化多线程软件程序的记录执行的性能和/或正确性特征。系统可以处理在执行多线程程序期间记录的基于块的信息，准备所记录信息的图形可视化，并以动画方式在显示器上显示图形可视化。系统可以允许观看者交互地控制动画图形可视化的显示。

6. 发明授权

US08862942B2 Method of system for detecting abnormal interleavings in concurrent programs 有权
标题翻译：在并发程序中检测异常交错的系统方法
公开(公告)号：US08862942B2
公开(公告)日：2014-10-14
申请号：US13498613
申请日：2011-09-29
申请人： Nicholas A. Jalbert , Cristiano L. Pereira , Gilles A. Pokam
发明人： Nicholas A. Jalbert , Cristiano L. Pereira , Gilles A. Pokam
IPC分类号： G06F11/00 , G06F11/36 , G06F11/14 , G06F9/38
CPC分类号： G06F11/1479 , G06F9/3851 , G06F11/3632
摘要： A method and system for detecting abnormal interleavings in a multi-threaded program includes generating an execution log in response to execution of the multi-threaded program. Based on the execution log, a list of allowable immediate interleavings is generated if the execution of the multi-threaded program resulted in no concurrency errors and a list of suspicious immediate interleavings is generated if the execution of the multi-threaded program resulted in one or more concurrency errors. The first and second lists are compared to generate a list of error-causing immediate interleavings. A replayable core is then generated and executed based on the list of error-causing immediate interleavings.
摘要翻译：一种用于检测多线程程序中的异常交织的方法和系统，包括响应于多线程程序的执行而生成执行日志。基于执行日志，如果多线程程序的执行导致没有并发错误，并且如果多线程程序的执行导致一个或多个程序执行，则生成可疑立即交织列表，则生成允许的立即交织的列表更多的并发错误。将第一和第二列表进行比较以产生造成误差的立即交错的列表。然后基于造成错误的即时交错的列表来生成并执行可重放的核心。

7. 发明申请

US20130297978A1 METHOD OF SYSTEM FOR DETECTING ABNORMAL INTERLEAVINGS IN CONCURRENT PROGRAMS 有权
标题翻译：用于检测同步程序中异常交互的系统方法
公开(公告)号：US20130297978A1
公开(公告)日：2013-11-07
申请号：US13498613
申请日：2011-09-29
申请人： Nicholas A. Jalbert , Cristiano L. Pereira , Gilles A. Pokam
发明人： Nicholas A. Jalbert , Cristiano L. Pereira , Gilles A. Pokam
IPC分类号： G06F11/14
CPC分类号： G06F11/1479 , G06F9/3851 , G06F11/3632
摘要： A method and system for detecting abnormal interleavings in a multi-threaded program includes generating an execution log in response to execution of the multi-threaded program. Based on the execution log, a list of allowable immediate interleavings is generated if the execution of the multi-threaded program resulted in no concurrency errors and a list of suspicious immediate interleavings is generated if the execution of the multi-threaded program resulted in one or more concurrency errors. The first and second lists are compared to generate a list of error-causing immediate interleavings. A replayable core is then generated and executed based on the list of error-causing immediate interleavings.
摘要翻译：一种用于检测多线程程序中的异常交织的方法和系统，包括响应于多线程程序的执行而生成执行日志。基于执行日志，如果多线程程序的执行导致没有并发错误，并且如果多线程程序的执行导致一个或多个程序执行，则生成可疑立即交织列表，则生成允许的立即交织的列表更多的并发错误。将第一和第二列表进行比较以产生造成误差的立即交错的列表。然后基于造成错误的即时交错的列表来生成并执行可重放的核心。

8. 发明授权

US09558118B2 Tracing mechanism for recording shared memory interleavings on multi-core processors 有权
标题翻译：用于在多核处理器上记录共享内存交错的跟踪机制
公开(公告)号：US09558118B2
公开(公告)日：2017-01-31
申请号：US13997747
申请日：2012-03-30
申请人： Gilles A. Pokam , Cristiano L. Pereira
发明人： Gilles A. Pokam , Cristiano L. Pereira , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00 , G06F12/08 , G06F9/30 , G06F11/36 , G06F12/02 , G06F13/16 , G11C7/10
CPC分类号： G06F12/0815 , G06F9/30043 , G06F11/3636 , G06F12/023 , G06F13/1663 , G06F2212/622 , G11C7/1072 , Y02D10/14
摘要： A memory race recorder (MRR) is provided. The MRR includes a multi-core processor having a relaxed memory consistency model, an extension to the multi-core processor, the extension to store chunks, the chunk having a chunk size (CS) and an instruction count (IC), and a plurality of cores to execute instructions. The plurality of cores executes load/store instructions to/from a store buffer (STB) and a simulated memory to store the value when the value is not in the STB. The oldest value in the STB is transferred to the simulated memory when the IC is equal to zero and the CS is greater than zero. The MRR logs a trace entry comprising the CS, the IC, and a global timestamp, the global timestamp proving a total order across all logged chunks.
摘要翻译：提供了一个记忆体记录仪（MRR）。 MRR包括具有放松的存储器一致性模型的多核处理器，多核处理器的扩展，存储块的扩展，具有块大小（CS）和指令计数（IC）的块，以及多个的核心执行指令。多个核对存储缓冲器（STB）和模拟存储器执行加载/存储指令以在值不在STB中时存储该值。当IC等于零并且CS大于零时，STB中的最旧值被传送到模拟存储器。 MRR记录包含CS，IC和全局时间戳的跟踪条目，全局时间戳记证明所有记录的块的总顺序。

9. 发明申请

US20150277967A1 Enabling Maximum Concurrency In A Hybrid Transactional Memory System 有权
标题翻译：在混合事务内存系统中启用最大并发性
公开(公告)号：US20150277967A1
公开(公告)日：2015-10-01
申请号：US14225804
申请日：2014-03-26
申请人： Irina Calciu , Justin E. Gottschlich , Tatiana Shpeisman , Gilles A. Pokam
发明人： Irina Calciu , Justin E. Gottschlich , Tatiana Shpeisman , Gilles A. Pokam
IPC分类号： G06F9/46 , G06F12/10
CPC分类号： G06F9/467 , G06F9/528
摘要： In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.
摘要翻译：在事务性存储器系统的实施例中，一种装置包括处理器和执行逻辑，以使得能够并行执行第一软件交易模式和第二软件交易模式的第二软件交易的至少一个第一软件交易，并且至少一个第一硬件事务模式的硬件事务和第二硬件事务模式的至少一个第二硬件事务。在一个示例中，执行逻辑可以在处理器内实现。描述和要求保护其他实施例。

10. 发明申请

US20150186178A1 Processor With Transactional Capability and Logging Circuitry To Report Transactional Operations 有权
标题翻译：具有事务功能和记录电路的处理器来报告事务操作
公开(公告)号：US20150186178A1
公开(公告)日：2015-07-02
申请号：US14142475
申请日：2013-12-27
申请人： Rolf Kassa , Justin E. Gottschlich , Shiliang Hu , Gilles A. Pokam , Robert C. Knauerhase
发明人： Rolf Kassa , Justin E. Gottschlich , Shiliang Hu , Gilles A. Pokam , Robert C. Knauerhase
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F9/528 , G06F11/0724 , G06F11/0772
摘要： A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.
摘要翻译：描述了一种处理器，其包括存储器访问冲突检测电路，以识别与正在由线程执行的事务有关的冲突，该线程相信它已经将信息锁定在存储器内。如果存储器访问冲突检测电路识别导致事务中止的冲突，则处理器还包括记录电路来构造和报告数据包。

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