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1. 发明申请

US20130055033A1 HARDWARE-ASSISTED PROGRAM TRACE COLLECTION WITH SELECTABLE CALL-SIGNATURE CAPTURE 审中-公开
标题翻译：硬件辅助程序跟踪采集与可选择的呼叫签名捕获
公开(公告)号：US20130055033A1
公开(公告)日：2013-02-28
申请号：US13300863
申请日：2011-11-21
申请人： Giles R. Frazier , David S. Levitan , Brian R. Mestan , Mauricio J. Serrano
发明人： Giles R. Frazier , David S. Levitan , Brian R. Mestan , Mauricio J. Serrano
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/348 , G06F11/3636 , G06F2201/83 , G06F2201/865
摘要： Hardware-assisted program tracing is facilitated by a processor that includes a root instruction address register, a program trace signature computation unit and a call signature register. When a program instruction having an address matching the root instruction address register is executed, a program trace signature is captured in the call signature register and capture of branch history is commenced. By accumulating different values of the call signature register, for example in response to an interrupt generated when the root instruction is executed, software that performs program tracing can obtain signatures of all of the multiple execution paths that lead to the root instruction, which is also specified by software in order to set different root instructions for program tracing. In an alternative implementation, a storage for multiple call signatures is provided in the processor and read at once by the software.
摘要翻译：硬件辅助程序跟踪由包括根指令地址寄存器，程序跟踪签名计算单元和呼叫签名寄存器的处理器来促进。当执行具有与根指令地址寄存器匹配的地址的程序指令时，在呼叫签名寄存器中捕获程序跟踪签名，并且开始分支历史记录的捕获。通过累积呼叫签名寄存器的不同值，例如响应于执行根指令时产生的中断，执行程序跟踪的软件可以获得导致根指令的所有多个执行路径的签名，这也是由软件指定，以便为程序跟踪设置不同的根指令。在替代实现中，在处理器中提供用于多个呼叫签名的存储器，并由软件一次读取。

2. 发明申请

US20120254837A1 TASK SWITCH IMMUNIZED PERFORMANCE MONITORING 有权
标题翻译：任务切换免疫性能监控
公开(公告)号：US20120254837A1
公开(公告)日：2012-10-04
申请号：US13079189
申请日：2011-04-04
申请人： GILES R. FRAZIER , David S. Levitan , Brian R. Mestan
发明人： GILES R. FRAZIER , David S. Levitan , Brian R. Mestan
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F2201/865
摘要： A performance monitoring technique provides task-switch immune operation without requiring storage and retrieval of the performance monitor state when a task switch occurs. When a hypervisor signals that a task is being resumed, it provides an indication, which starts a delay timer. The delay timer is resettable in case a predetermined time period has not elapsed when the next task switch occurs. After the delay timer expires, analysis of the performance monitor measurements is resumed, which prevents an initial state or a state remaining from a previous task from corrupting the performance monitoring results. The performance monitor may be or include an execution trace unit that collects taken branches in a current trace and may use branch prediction success to determine whether to collect a predicted and taken branch instruction in a current trace or to start a new segment when the branch resolves in a non-predicted direction.
摘要翻译：性能监控技术提供任务切换免疫操作，而不需要在发生任务切换时存储和检索性能监视器状态。当管理程序发出任务正在恢复的信号时，它提供指示，启动一个延迟定时器。在发生下一任务切换的情况下，在没有经过预定时间段的情况下，可以将延迟定时器复位。在延迟定时器到期后，恢复对性能监视器测量的分析，这阻止了先前任务的初始状态或状态损坏性能监视结果。性能监视器可以是或包括执行跟踪单元，其在当前跟踪中收集所采取的分支，并且可以使用分支预测成功来确定是否在当前跟踪中收集预测和采取的分支指令，或者当分支解析时启动新分段处于非预测方向。

3. 发明授权

US08868886B2 Task switch immunized performance monitoring 有权
标题翻译：任务开关免疫性能监测
公开(公告)号：US08868886B2
公开(公告)日：2014-10-21
申请号：US13079189
申请日：2011-04-04
申请人： Giles R. Frazier , David S. Levitan , Brian R. Mestan
发明人： Giles R. Frazier , David S. Levitan , Brian R. Mestan
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F2201/865
摘要： A performance monitoring technique provides task-switch immune operation without requiring storage and retrieval of the performance monitor state when a task switch occurs. When a hypervisor signals that a task is being resumed, it provides an indication, which starts a delay timer. The delay timer is resettable in case a predetermined time period has not elapsed when the next task switch occurs. After the delay timer expires, analysis of the performance monitor measurements is resumed, which prevents an initial state or a state remaining from a previous task from corrupting the performance monitoring results. The performance monitor may be or include an execution trace unit that collects taken branches in a current trace and may use branch prediction success to determine whether to collect a predicted and taken branch instruction in a current trace or to start a new segment when the branch resolves in a non-predicted direction.
摘要翻译：性能监控技术提供任务切换免疫操作，而不需要在发生任务切换时存储和检索性能监视器状态。当管理程序发出任务正在恢复的信号时，它提供指示，启动一个延迟定时器。在发生下一任务切换的情况下，在没有经过预定时间段的情况下，可以将延迟定时器复位。在延迟定时器到期后，恢复对性能监视器测量的分析，这阻止了先前任务的初始状态或状态损坏性能监视结果。性能监视器可以是或包括执行跟踪单元，其在当前跟踪中收集所采取的分支，并且可以使用分支预测成功来确定是否在当前跟踪中收集预测和采取的分支指令，或者当分支解析时启动新分段处于非预测方向。

4. 发明申请

US20120005462A1 Hardware Assist for Optimizing Code During Processing 审中-公开
标题翻译：处理过程中优化代码的硬件辅助
公开(公告)号：US20120005462A1
公开(公告)日：2012-01-05
申请号：US12828697
申请日：2010-07-01
申请人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
发明人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F9/3808 , G06F9/3844 , G06F11/348 , G06F2201/88
摘要： A method, data processing system, and computer program product for obtaining information about instructions. Instructions are processed. In response to processing a branch instruction in the instructions, a determination is made as to whether a result from processing the branch instruction follows a prediction of whether a branch is predicted to occur for the branch instruction. In response to the result following the prediction, the branch instruction is added to a current segment in a trace. In response to an absence of the result following the prediction, the branch instruction is added to the current segment in the trace and a first new segment and a second new segment are created. The first new segment includes a first branch instruction reached in the instructions from following the prediction. The second new segment includes a second branch instruction in the instructions reached from not following the prediction.
摘要翻译：一种用于获取关于指令的信息的方法，数据处理系统和计算机程序产品。处理说明。响应于在指令中处理分支指令，确定来自处理分支指令的结果是否遵循预测分支指令是否为分支指令发生的预测。响应于预测结果，分支指令被添加到跟踪中的当前段。响应于预测之后没有结果，分支指令被添加到跟踪中的当前段，并且创建第一新段和第二新段。第一个新的段包括在跟随预测的指令中达到的第一个分支指令。第二个新的段包括从不遵循预测到达的指令中的第二个分支指令。

5. 发明授权

US08131976B2 Tracking effective addresses in an out-of-order processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US08131976B2
公开(公告)日：2012-03-06
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

6. 发明授权

US09069563B2 Reducing store-hit-loads in an out-of-order processor 有权
标题翻译：减少无序处理器中的存储命中负载
公开(公告)号：US09069563B2
公开(公告)日：2015-06-30
申请号：US13235174
申请日：2011-09-16
申请人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
发明人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/3838
摘要： A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
摘要翻译：用于减少无序处理器中的存储命中负载的技术包括存储与存储命中加载（SHL）管线冲洗相关联的存储指令的存储地址在SHL条目中。响应于检测存储地址的另一个SHL管道flush，更新与SHL条目相关联的当前计数。响应于与SHL条目相关联的当前计数到达第一终端计数，创建存储指令的依赖关系，使得具有与存储地址重叠的加载地址的较年轻加载指令的执行停止，直到存储指令执行。

7. 发明申请

US20130073833A1 REDUCING STORE-HIT-LOADS IN AN OUT-OF-ORDER PROCESSOR 有权
标题翻译：减少订单处理器中的存储负载
公开(公告)号：US20130073833A1
公开(公告)日：2013-03-21
申请号：US13235174
申请日：2011-09-16
申请人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
发明人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3834 , G06F9/3838
摘要： A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
摘要翻译：用于减少无序处理器中的存储命中负载的技术包括存储与存储命中加载（SHL）管线冲洗相关联的存储指令的存储地址在SHL条目中。响应于检测存储地址的另一个SHL管道flush，更新与SHL条目相关联的当前计数。响应于与SHL条目相关联的当前计数到达第一终端计数，创建存储指令的依赖关系，使得具有与存储地址重叠的加载地址的较年轻加载指令的执行停止，直到存储指令执行。

8. 发明申请

US20100262806A1 Tracking Effective Addresses in an Out-of-Order Processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US20100262806A1
公开(公告)日：2010-10-14
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

9. 发明授权

US07844807B2 Branch target address cache storing direct predictions 失效
标题翻译：分支目标地址缓存存储直接预测
公开(公告)号：US07844807B2
公开(公告)日：2010-11-30
申请号：US12024197
申请日：2008-02-01
申请人： David S. Levitan , Lixin Zhang
发明人： David S. Levitan , Lixin Zhang
IPC分类号： G06F9/35 , G06F9/355 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit and instruction sequencing logic that fetches instructions for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address cache (BTAC) having at least one direct entry providing storage for a direct branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address immediately after the first instruction fetch address and at least one indirect entry providing storage for an indirect branch target address prediction associating a third instruction fetch address with a branch target address to be used as a fourth instruction fetch address subsequent to both the third instruction fetch address and an intervening fifth instruction fetch address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元和指令排序逻辑，其提取由执行单元执行的指令。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括分支目标地址高速缓存（BTAC），其具有至少一个直接条目，为直接分支目标地址预测提供存储，该直接分支目标地址预测将第一指令获取地址与分支目标地址相关联，以将分配目标地址紧随在第二指令获取地址之后第一指令获取地址和至少一个间接条目提供用于间接分支目标地址预测的存储，用于将第三指令获取地址与分支目标地址相关联，以将分配目标地址用作第三指令提取地址和中间地址之后的第四指令获取地址第五指令提取地址。

10. 发明授权

US07809933B2 System and method for optimizing branch logic for handling hard to predict indirect branches 有权
标题翻译：用于优化分支逻辑以处理难以预测间接分支的系统和方法
公开(公告)号：US07809933B2
公开(公告)日：2010-10-05
申请号：US11759350
申请日：2007-06-07
申请人： David S. Levitan , Wolfram Sauer
发明人： David S. Levitan , Wolfram Sauer
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/322 , G06F9/30181 , G06F9/3804
摘要： A system and method for optimizing the branch logic of a processor to improve handling of hard to predict indirect branches are provided. The system and method leverage the observation that there will generally be only one move to the count register (mtctr) instruction that will be executed while a branch on count register (bcctr) instruction has been fetched and not executed. With the mechanisms of the illustrative embodiments, fetch logic detects that it has encountered a bcctr instruction that is hard to predict and, in response to this detection, blocks the target fetch from entering the instruction buffer of the processor. At this point, the fetch logic has fetched all the instructions up to and including the bcctr instruction but no target instructions. When the next mtctr instruction is executed, the branch logic of the processor grabs the data and starts fetching using that target address. Since there are no other target instructions that were fetched, no flush is needed if that target address is the correct address, i.e. the branch prediction is correct.
摘要翻译：提供了一种用于优化处理器的分支逻辑以改善难以预测间接分支的处理的系统和方法。系统和方法利用这样的观察，通常只有一个移动到计数寄存器（mtctr）指令，在计数寄存器（bcctr）指令的分支已经被取出并且不被执行时将被执行。利用说明性实施例的机制，提取逻辑检测到它已经遇到难以预测的bcctr指令，并且响应于该检测阻止目标提取进入处理器的指令缓冲器。此时，提取逻辑已经获取了直到并包括bcctr指令但没有目标指令的所有指令。当执行下一个mtctr指令时，处理器的分支逻辑抓取数据，并使用该目标地址开始提取。由于没有其他目标指令被取出，如果目标地址是正确的地址，即分支预测是正确的，则不需要刷新。

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