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1. 发明授权

US06716689B2 MOS transistor having a T-shaped gate electrode and method for fabricating the same 失效
公开(公告)号：US06716689B2
公开(公告)日：2004-04-06
申请号：US10274035
申请日：2002-10-21
申请人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Sang-Su Kim , Jung-Il Lee
发明人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Sang-Su Kim , Jung-Il Lee
IPC分类号： H01L21338
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

2. 发明授权

US06881650B2 Method for forming SOI substrate 有权
标题翻译： SOI衬底的形成方法
公开(公告)号：US06881650B2
公开(公告)日：2005-04-19
申请号：US10307351
申请日：2002-12-02
申请人： Jung-Il Lee , Kazuyuki Fujihara , Nae-In Lee , Geum-Jong Bae , Hwa-Sung Rhee , Sang-su Kim
发明人： Jung-Il Lee , Kazuyuki Fujihara , Nae-In Lee , Geum-Jong Bae , Hwa-Sung Rhee , Sang-su Kim
IPC分类号： H01L21/205 , H01L21/02 , H01L21/20 , H01L21/30 , H01L21/46 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76254
摘要： A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a porous silicon-germanium layer thereon. A silicon-germanium epitaxial layer is formed on the porous silicon-germanium layer, an oxide layer is formed on a second silicon substrate, the second silicon substrate is bonded where the oxide layer is formed to the first silicon substrate where the silicon-germanium epitaxial layer is formed. Layers are removed to expose the silicon-germanium epitaxial layer and a strained silicon epitaxial layer is formed thereon. The porous silicon-germanium layer prevents lattice defects of the relaxed silicon-germanium layer from transferring to the silicon-germanium epitaxial layer. Therefore, it is possible to form the silicon-germanium layer and the strained silicon layer of the SOI layer without defects.
摘要翻译：一种用于形成包括含有锗的SOI层和设置在SOI层上的应变硅层的SOI衬底的方法包括：使用外延生长方法在第一硅衬底上形成松弛的硅 - 锗层，并且形成多孔硅 - 锗层上。在多孔硅锗层上形成硅 - 锗外延层，在第二硅衬底上形成氧化物层，将形成氧化物层的第二硅衬底接合到第一硅衬底上，其中硅 - 锗外延形成层。去除层以暴露硅 - 锗外延层，并在其上形成应变硅外延层。多孔硅 - 锗层防止松散的硅 - 锗层的晶格缺陷转移到硅 - 锗外延层。因此，可以形成SOI层的硅 - 锗层和应变硅层，而没有缺陷。

3. 发明授权

US07250655B2 MOS transistor having a T-shaped gate electrode 失效
标题翻译： MOS晶体管具有T形栅电极
公开(公告)号：US07250655B2
公开(公告)日：2007-07-31
申请号：US10659384
申请日：2003-09-11
申请人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Sang-Su Kim , Jung-II Lee
发明人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Sang-Su Kim , Jung-II Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.
摘要翻译：提供具有T形栅电极的MOS晶体管及其制造方法，其中MOS晶体管包括在半导体衬底上的T形栅电极; 设置在所述栅极电极的两侧以覆盖所述半导体衬底的顶表面的L形下间隔件; 以及形成在栅极两侧的半导体衬底中的低，中，高浓度杂质区。高浓度杂质区设置在与下隔片相邻的半导体衬底中，并且中浓度杂质区设置在高浓度杂质区和低浓度杂质区之间。根据本发明的MOS晶体管提供了电容的减小，沟道长度的减小以及栅电极的横截面面积的增加。同时，中等浓度杂质区域提供了源极/漏极电阻R sd 的降低。

4. 发明授权

US06750532B2 CMOS semiconductor device and method of manufacturing the same 失效
标题翻译： CMOS半导体器件及其制造方法
公开(公告)号：US06750532B2
公开(公告)日：2004-06-15
申请号：US10336604
申请日：2003-01-03
申请人： Hwa-Sung Rhee , Geum-Jong Bae , Tae-Hee Choe , Sang-Su Kim , Nae-In Lee
发明人： Hwa-Sung Rhee , Geum-Jong Bae , Tae-Hee Choe , Sang-Su Kim , Nae-In Lee
IPC分类号： H01L29167
CPC分类号： H01L21/2807 , H01L21/823842
摘要： In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.
摘要翻译：在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分中的Ge浓度低于10 ％。

5. 发明授权

US06917085B2 Semiconductor transistor using L-shaped spacer 有权
标题翻译：半导体晶体管采用L型间隔器
公开(公告)号：US06917085B2
公开(公告)日：2005-07-12
申请号：US10728811
申请日：2003-12-08
申请人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Young-Gun Ko , Tae-Hee Choe , Sang-Su Kim
发明人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Young-Gun Ko , Tae-Hee Choe , Sang-Su Kim
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66598 , H01L29/66507 , H01L29/66515 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.
摘要翻译：本发明提供一种使用L形间隔物的半导体晶体管。半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三间隔物。在第三间隔物和栅极图案之间以及在第三间隔物和基底之间形成L形的第四间隔物。高浓度接合区域位于第三间隔物之外的基板中，并且低浓度接合区域位于第三间隔物的水平突出部分的下方。中等浓度接合区域位于高浓度和低浓度接合区域之间。

6. 发明授权

US06524902B2 Method of manufacturing CMOS semiconductor device 失效
标题翻译：制造CMOS半导体器件的方法
公开(公告)号：US06524902B2
公开(公告)日：2003-02-25
申请号：US10001619
申请日：2001-10-23
申请人： Hwa-Sung Rhee , Geum-Jong Bae , Tae-Hee Choe , Sang-Su Kim , Nae-In Lee
发明人： Hwa-Sung Rhee , Geum-Jong Bae , Tae-Hee Choe , Sang-Su Kim , Nae-In Lee
IPC分类号： H01L218238
CPC分类号： H01L21/2807 , H01L21/823842
摘要： In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.
摘要翻译：在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分Ge浓度低于10 ％。

7. 发明授权

US06881621B2 Method of fabricating SOI substrate having an etch stop layer, and method of fabricating SOI integrated circuit using the same 有权
标题翻译：制造具有蚀刻停止层的SOI衬底的方法，以及使用其制造SOI集成电路的方法
公开(公告)号：US06881621B2
公开(公告)日：2005-04-19
申请号：US10713216
申请日：2003-11-17
申请人： Tae-Hee Choe , Nae-In Lee , Geum-Jong Bae , Sang-Su Kim , Hwa-Sung Rhee
发明人： Tae-Hee Choe , Nae-In Lee , Geum-Jong Bae , Sang-Su Kim , Hwa-Sung Rhee
IPC分类号： H01L27/04 , H01L21/00 , H01L21/02 , H01L21/68 , H01L21/74 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/62 , H01L27/01 , H01L27/02 , H01L27/06 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/00 , H01L29/72 , H01L31/0392
CPC分类号： H01L21/6835 , H01L21/743 , H01L21/8221 , H01L21/84 , H01L27/0251 , H01L27/0688 , H01L27/1203 , H01L2221/68363 , H01L2924/30105
摘要： A method of fabricating a SOI substrate includes sequentially forming a first semiconductor layer, which may be either a porous semiconductor layer or a bubble layer, a second semiconductor layer and a buried oxide layer on a front surface of a semiconductor substrate, forming an etch stopping layer, which may be a silicon nitride layer, on a front surface of a supporting substrate; contacting the etch stopping layer with the buried oxide layer to bond the semiconductor substrate to the supporting substrate; and selectively removing the semiconductor substrate and the first semiconductor layer to expose the second semiconductor layer. The method may additionally include forming a buffer oxide layer between the supporting substrate and the etch stopping layer.
摘要翻译：制造SOI衬底的方法包括在半导体衬底的前表面上顺序地形成可以是多孔半导体层或气泡层的第一半导体层，第二半导体层和掩埋氧化物层，形成蚀刻停止层，其可以是氮化硅层;在支撑衬底的前表面上; 使所述蚀刻停止层与所述掩埋氧化物层接触以将所述半导体衬底接合到所述支撑衬底; 以及选择性地去除所述半导体衬底和所述第一半导体层以暴露所述第二半导体层。该方法还可以包括在支撑衬底和蚀刻停止层之间形成缓冲氧化物层。

8. 发明授权

US06806517B2 Flash memory having local SONOS structure using notched gate and manufacturing method thereof 失效
标题翻译：具有本地SONOS结构的闪存，使用缺口栅极及其制造方法
公开(公告)号：US06806517B2
公开(公告)日：2004-10-19
申请号：US10388427
申请日：2003-03-17
申请人： Sang Su Kim , Nae-In Lee , Geum-Jong Bae , Ki Chul Kim , Hwa Sung Rhee
发明人： Sang Su Kim , Nae-In Lee , Geum-Jong Bae , Ki Chul Kim , Hwa Sung Rhee
IPC分类号： H01L2710
CPC分类号： H01L29/4232 , H01L21/28114 , H01L21/28273 , H01L21/28282 , H01L29/66833 , H01L29/7923
摘要： A notched gate SONOS transistor includes: a substrate having source/drain regions; a gate insulator layer on the substrate between the source/drain regions; a notched gate structure, on the gate insulator leyer, having at least one notch; and at least one ONO wedge structure in the at least one notch, respectively, of the gate structure.
摘要翻译：缺口门SONOS晶体管包括：具有源/漏区的衬底; 在源/漏区之间的衬底上的栅极绝缘体层; 在所述栅极绝缘体雷管上具有至少一个凹口的缺口栅极结构; 以及分别在所述栅极结构的所述至少一个凹口中的至少一个ONO楔形结构。

9. 发明授权

US06670677B2 SOI substrate having an etch stop layer and an SOI integrated circuit fabricated thereon 有权
标题翻译： SOI衬底具有在其上制造的蚀刻停止层和SOI集成电路
公开(公告)号：US06670677B2
公开(公告)日：2003-12-30
申请号：US09989112
申请日：2001-11-21
申请人： Tae-Hee Choe , Nae-In Lee , Geum-Jong Bae , Sang-Su Kim , Hwa-Sung Rhee
发明人： Tae-Hee Choe , Nae-In Lee , Geum-Jong Bae , Sang-Su Kim , Hwa-Sung Rhee
IPC分类号： H01L2972
CPC分类号： H01L21/6835 , H01L21/743 , H01L21/8221 , H01L21/84 , H01L27/0251 , H01L27/0688 , H01L27/1203 , H01L2221/68363 , H01L2924/30105
摘要： A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer and a semiconductor layer sequentially stacked on the etch stopping layer. The etch stopping layer preferably has an etch selectivity with respect to the buried oxide layer. A device isolation layer is preferably formed to define active regions. The device isolation, buried oxide and etch-stop layers are selectively removed to form first and second holes exposing the supporting substrate without damaging it. Semiconductor epitaxial layers grown on the exposed supporting substrate therefore have single crystalline structures without crystalline defects. Thus, when impurity regions are formed at surfaces of the epitaxial layers, a high performance PN diode having a superior leakage current characteristic may be formed.
摘要翻译：提供了具有蚀刻停止层的SOI衬底，在SOI衬底上制造的SOI集成电路，以及制造两者的方法。 SOI衬底包括支撑衬底，沉积在支撑衬底上的蚀刻停止层，依次层叠在蚀刻停止层上的掩埋氧化物层和半导体层。蚀刻停止层优选地相对于掩埋氧化物层具有蚀刻选择性。优选形成器件隔离层以限定有源区。选择性地去除器件隔离，掩埋氧化物和蚀刻停止层，以形成暴露支撑衬底的第一和第二孔而不损坏支撑衬底。因此，在暴露的支撑衬底上生长的半导体外延层具有没有结晶缺陷的单晶结构。因此，当在外延层的表面形成杂质区时，可以形成具有优异的漏电流特性的高性能PN二极管。

10. 发明授权

US06794306B2 Semiconductor device having gate all around type transistor and method of forming the same 有权
标题翻译：具有栅极全周型晶体管的半导体器件及其形成方法
公开(公告)号：US06794306B2
公开(公告)日：2004-09-21
申请号：US10463554
申请日：2003-06-17
申请人： Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
发明人： Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78654 , Y10S438/933
摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.
摘要翻译：公开了具有栅极全部（GAA）型晶体管的半导体器件及其制造方法。制备由SOI层，掩埋氧化物层和下基板构成的SOI衬底。 SOI层具有硅锗层和硅层的至少一个单元双层。图案化SOI层，以形成一定方向的有源层图案。形成绝缘层以覆盖有源层图案。在覆盖有绝缘层的有源层图案上堆叠蚀刻停止层。蚀刻停止层被图案化并在沟道区域与有源层图案交叉的栅极区域去除。绝缘层在栅极区域被去除。硅锗层被各向同性地蚀刻并选择性地去除以在有源层图案的沟道区域形成空腔。在选择性地去除硅锗层的状态下，形成栅极绝缘层以覆盖有源层图案的暴露表面。通过化学气相沉积（CVD）将栅极导电层层叠在基板上，以填充包括空腔的栅极区域。有源层图案的沟道区域的中间部分可以被图案化以被划分成一行形成的多个图案。

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