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1. 发明授权

US06262448B1 Memory cell having trench capacitor and vertical, dual-gated transistor 失效
标题翻译：存储单元具有沟槽电容器和垂直双门控晶体管
公开(公告)号：US06262448B1
公开(公告)日：2001-07-17
申请号：US09302756
申请日：1999-04-30
申请人： Gerhard Enders , Matthias Ilg , Lothar Risch , Dietrich Widmann
发明人： Gerhard Enders , Matthias Ilg , Lothar Risch , Dietrich Widmann
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell. With such an arrangement a DRAM cell is provided having a relatively occupies a relatively small amount of surface area of the semiconductor body.
摘要翻译： DRAM单元设置在半导体本体的电隔离区域中。电池包括设置在沟槽中的存储电容器。电容器完全设置在半导体本体的隔离区域内。电池包括设置在隔离区域中的晶体管。晶体管有一对门。提供字线用于寻址单元。字线具有到晶体管的电接触区域。字线接触区域完全设置在半导体本体的隔离区域内。晶体管有一个有源区。有源区域有源极，漏极和沟道区域。有源区域完全设置在半导体本体的隔离区域内。为单元提供位线。位线在一对位线接触区域与晶体管的栅极电接触。两个这样的位线接触区域完全设置在电池的隔离区域内。通过这样的布置，提供了DRAM单元，其具有相对占据半导体本体的较小量的表面积。

2. 发明授权

US06503784B1 Double gated transistor 有权
标题翻译：双门控晶体管
公开(公告)号：US06503784B1
公开(公告)日：2003-01-07
申请号：US09670742
申请日：2000-09-27
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L218238
CPC分类号： H01L27/11 , H01L21/823885 , H01L27/092 , H01L27/1104 , H01L27/1203
摘要： A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：一种具有一对垂直双门控CMOS晶体管的半导体体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

3. 发明授权

US06472767B1 Static random access memory (SRAM) 有权
标题翻译：静态随机存取存储器（SRAM）
公开(公告)号：US06472767B1
公开(公告)日：2002-10-29
申请号：US09302757
申请日：1999-04-30
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104
摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：具有一对垂直双门控CMOS晶体管的半导体本体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

4. 发明授权

US06459123B1 Double gated transistor 有权
标题翻译：双门控晶体管
公开(公告)号：US06459123B1
公开(公告)日：2002-10-01
申请号：US09302768
申请日：1999-04-30
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L2994
CPC分类号： H01L27/11 , H01L21/823885 , H01L27/092 , H01L27/1104 , H01L27/1203
摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：具有一对垂直双门控CMOS晶体管的半导体本体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

5. 发明授权

US07180115B1 DRAM cell structure with tunnel barrier 有权
标题翻译：具有隧道势垒的DRAM单元结构
公开(公告)号：US07180115B1
公开(公告)日：2007-02-20
申请号：US10130441
申请日：2000-11-14
申请人： Franz Hofmann , Wolfgang Roesner , Lothar Risch , Till Schloesser
发明人： Franz Hofmann , Wolfgang Roesner , Lothar Risch , Till Schloesser
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10891 , H01L27/1203
摘要： The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.
摘要翻译：本发明涉及一种具有第一源极/漏极区域（S / D 1），与其相邻的沟道区域（KA），与其相邻的第二源极/漏极区域（S / D 2），栅极电介质和栅电极。电容器的第一电容器电极（SP）连接到第一源极/漏极区域（S / D 1）。绝缘结构完全围绕电路装置的绝缘区域。至少第一电容器电极（SP）和第一源极/漏极区域（S / D 1）布置在绝缘区域中。电容器的第二源极/漏极区域（S / D 2）和第二电容器电极布置在绝缘区域的外部。绝缘结构防止第一电容器电极（SP）通过电容器的充电和放电之间的泄漏电流而失去电荷。布置在通道区域（KA）中的隧道势垒（T）是绝缘结构的一部分。将第一电容器电极（SP）与第二电容器电极分离的电容器电介质（KD）是绝缘结构的一部分。

6. 发明授权

US06600200B1 MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors 有权
标题翻译： MOS晶体管，制造MOS晶体管的方法和制造两个互补MOS晶体管的方法
公开(公告)号：US06600200B1
公开(公告)日：2003-07-29
申请号：US09645762
申请日：2000-08-25
申请人： Bernhard Lustig , Herbert Schäfer , Lothar Risch
发明人： Bernhard Lustig , Herbert Schäfer , Lothar Risch
IPC分类号： H01L2906
CPC分类号： H01L21/823807 , H01L21/74 , H01L29/1083
摘要： A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.
摘要翻译： MOS晶体管及其制造方法包括在半导体衬底中制造由第一导电类型掺杂的阱。掺杂浓度小于1017cm-3的外延层设置在掺杂阱的表面上。由第二导电类型掺杂的与第一导电类型相反的源极/漏极区和沟道区设置在外延层中，并且它们的深度小于或等于外延层的厚度。还提供了制造两个互补MOS晶体管的方法。

7. 发明授权

US06553157B2 Optoelectronic microelectronic system 有权
公开(公告)号：US06553157B2
公开(公告)日：2003-04-22
申请号：US10093320
申请日：2002-03-07
申请人： Thomas Schultz , Wolfgang Rösner , Lothar Risch
发明人： Thomas Schultz , Wolfgang Rösner , Lothar Risch
IPC分类号： G02B612
CPC分类号： H01L31/0232 , H01L27/1443
摘要： In an integrated optoelectronic microelectronic system, an optoelectronically active diode part is formed in a semiconductor substrate by zones forming depletion layers. The system is provided in a mesa that stands vertically on a semiconductor substrate and runs in a direction of extension thereof. A light waveguide is optically coupled to the diode part in such a way that light is coupled into the diode part via the mesa side wall.

8. 发明授权

US06518628B1 Integrated CMOS circuit configuration, and production of same 有权
标题翻译：集成CMOS电路配置，生产相同
公开(公告)号：US06518628B1
公开(公告)日：2003-02-11
申请号：US09423864
申请日：1999-11-15
申请人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
发明人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
IPC分类号： H01L2976
CPC分类号： H01L27/0922
摘要： An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.
摘要翻译：一种集成CMOS电路装置及其制造方法，其包括第一MOS晶体管和与其互补的第二MOS晶体管，其中MOS晶体管中的一个布置在沟槽的底部，而另一个布置在主表面的半导体衬底。 MOS晶体管相对于彼此布置，使得流过MOS晶体管的电流分别基本上平行于布置在MOS晶体管之间的沟槽的侧壁。

9. 发明授权

US06255684B1 DRAM cell configuration and method for its production 失效
标题翻译： DRAM单元配置及其生产方法
公开(公告)号：US06255684B1
公开(公告)日：2001-07-03
申请号：US09071798
申请日：1998-05-04
申请人： Wolfgang Roesner , Lothar Risch , Franz Hofmann
发明人： Wolfgang Roesner , Lothar Risch , Franz Hofmann
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks, with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.
摘要翻译： DRAM单元配置包括每个存储单元的垂直MOS晶体管。晶体管的第一源极/漏极区域分别属于两个相邻的晶体管并与位线相邻。晶体管的第二源/漏区连接到存储节点。晶体管的栅电极具有由栅极氧化物邻接的正好两侧。可以通过使用具有4F2的存储单元面积的三个掩模来产生DRAM单元配置。 F是可以通过使用各自技术制造的最小结构尺寸。

10. 发明授权

US6037209A Method for producing a DRAM cellular arrangement 有权
标题翻译：用于制造DRAM蜂窝装置的方法
公开(公告)号：US6037209A
公开(公告)日：2000-03-14
申请号：US254696
申请日：1999-03-15
申请人： Wolfgang Rosner , Lothar Risch , Franz Hofmann , Reinhard Stengl
发明人： Wolfgang Rosner , Lothar Risch , Franz Hofmann , Reinhard Stengl
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The DRAM cell arrangement comprises, per memory cell, a vertical MOS transistor whose first source/drain region is connected to a storage node of a storage capacitor, whose channel region (3) is annularly enclosed by a gate electrode (13) and whose second source/drain region is connected to a buried bit line. The DRAM cell arrangement is produced using only two masks, with the aid of a spacer technique, with a memory cell area of 2F.sup.2, where F is the minimum structure size which can be produced using the respective technology.
摘要翻译： PCT No.PCT / DE97 / 01580 Sec。 371 1999年3月15日 102（e）1999年3月15日PCT 1997年7月28日PCT公布。出版物WO98 / 11604 日期1998年3月19日DRAM单元布置包括每个存储单元的垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储节点，其沟道区域（3）被栅电极环形封闭 13），并且其第二源极/漏极区域连接到掩埋位线。借助于间隔器技术，仅使用两个掩模来制造DRAM单元布置，存储单元面积为2F2，其中F是可以使用各自技术产生的最小结构尺寸。

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