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1. 发明授权

US06383864B1 Memory cell for dynamic random access memory (DRAM) 失效
公开(公告)号：US06383864B1
公开(公告)日：2002-05-07
申请号：US08940897
申请日：1997-09-30
申请人： Gerd Scheller , Martin Gall , Reinhard J. Stengl
发明人： Gerd Scheller , Martin Gall , Reinhard J. Stengl
IPC分类号： H01L218242
摘要： A memory cell, which includes a transistor and a capacitor, for use in a DRAM uses a silicon-filled vertical trench as the capacitor and a vertical transistor superposed over the vertical trench in a silicon chip. An epitaxial layer is formed at the top of the fill in the trench to impart seed information to the primarily polysilicon silicon fill in the trench. A polysilicon layer is deposited over the top surface of the chip, is apertured over the top of the trench, and has its sidewalls oxidized. The opening is then refilled with epitaxial silicon in which there is created in operation an inversion layer that serves as the channel of the transistor, and the deposited polysilicon layer serves as the word line. Another silicon layer is deposited over the epitaxial layer to serve as the bit line. The source/drain regions of the transistor are formed at the merger of the deposited layer with the fill in the trench and the merger with the polysilicon layer that serves as the bit line.

2. 发明授权

US5893735A Three-dimensional device layout with sub-groundrule features 失效
标题翻译：具有子基础特征的三维设备布局
公开(公告)号：US5893735A
公开(公告)日：1999-04-13
申请号：US742533
申请日：1996-11-01
申请人： Reinhard J. Stengl , Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Radhika Srinivasan , Alvin P. Short , Bernhard Poschenrieder
发明人： Reinhard J. Stengl , Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Radhika Srinivasan , Alvin P. Short , Bernhard Poschenrieder
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： Method for forming three-dimensional device structures comprising a second device having sub-groundrule features formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device. the sub-groundrule feature is formed using mandrel and spacers.
摘要翻译：公开了一种用于形成三维器件结构的方法，其包括在第一器件上形成的具有次基底特征的第二器件。在第一装置上方形成具有单一晶体顶表面的层，以提供用于形成第二装置的有效区域的基座。使用心轴和间隔件形成子底座特征。

3. 发明授权

US4883215A Method for bubble-free bonding of silicon wafers 失效
标题翻译：硅片无气泡接合的方法
公开(公告)号：US4883215A
公开(公告)日：1989-11-28
申请号：US286460
申请日：1988-12-19
申请人： Ulrich M. Goesele , Reinhard J. Stengl
发明人： Ulrich M. Goesele , Reinhard J. Stengl
IPC分类号： H01L21/18 , H01L21/20 , H01L21/306 , H01L21/58
CPC分类号： H01L21/02052 , H01L21/187 , H01L21/2007 , H01L24/26 , H01L24/83 , H01L2224/8319 , H01L2224/8385 , H01L2224/83894 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01077 , H01L2924/01082 , H01L2924/07802 , Y10S148/012 , Y10S228/903 , Y10S438/974
摘要： A method for bubble-free bonding of silicon wafers to silicon wafers or silicon wafers to quartz wafers either outside or inside a Clean Room. The method includes the steps of positioning wafers in closely spaced-apart and parallel relationship to each other in a rack or the like with mirror-polished surfaces of the wafers facing each other, cleansing the mirror-polished surfaces with a hydrophilization cleansing solution, flushing the cleansing solution from the mirror-polished surfaces of the wafers with deionized water, drying the wafers in a spin-dryer, and moving the wafers together so that contact occurs between opposing mirror-polished surfaces of the wafers and bonding occurs.
摘要翻译：一种在无尘室外部或内部将硅晶片与硅晶片或硅晶片无气泡接合到石英晶片的方法。该方法包括以下步骤：将晶片彼此间隔开并且平行的关系定位在机架等中，并将晶片的镜面抛光表面相互面对，用亲水化清洁溶液清洗镜面抛光表面，冲洗用去离子水从晶片的镜面抛光表面清洁溶液，在旋转干燥器中干燥晶片，并将晶片一起移动，使得在晶片的相对的镜面抛光表面之间发生接触，并发生接合。

4. 发明授权

US5627092A Deep trench dram process on SOI for low leakage DRAM cell 失效
标题翻译：用于低泄漏DRAM单元的SOI深沟槽工艺
公开(公告)号：US5627092A
公开(公告)日：1997-05-06
申请号：US313507
申请日：1994-09-26
申请人： Johann Alsmeier , Reinhard J. Stengl
发明人： Johann Alsmeier , Reinhard J. Stengl
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/786 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/1203
摘要： A deep trench DRAM cell is formed on a silicon on isolator (SOI) substrate, with a buried strap formed by outdiffusion of dopant in associated trench node material, for providing an electrical connection between the trench node and the active area of a MOS transfer gate formed in the substrate adjacent the trench in an uppermost portion of the substrate.
摘要翻译：在隔离器（SOI）衬底上的硅上形成深沟槽DRAM单元，其中通过相关沟槽节点材料中的掺杂剂的扩散扩散形成的掩埋带，用于在沟槽节点和MOS传输门的有源区之间提供电连接在衬底中邻近衬底的最上部形成的衬底。

5. 发明授权

US5543348A Controlled recrystallization of buried strap in a semiconductor memory device 失效
标题翻译：半导体存储器件中埋置带的可控再结晶
公开(公告)号：US5543348A
公开(公告)日：1996-08-06
申请号：US412442
申请日：1995-03-29
申请人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard J. Stengl
发明人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard J. Stengl
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861
摘要： A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate and an impurity-doped first conductive region is then formed by filling the trench with an impurity-doped first conductive material. The impurity-doped first conductive region is etched back to a first level within the trench. An insulating layer is then formed on a sidewall of the portion of the trench opened by the etching back of the impurity-doped first conductive region and a second conductive region is formed by filling the remainder of the trench with a second conductive material. The insulating layer and the second conductive region are etched back to a second level within the trench and an amorphous silicon layer is formed in the portion of the trench opened by the etching back of the insulating layer and the second conductive region. The undoped amorphous silicon layer is etched back to a third a level within the trench. The undoped amorphous silicon layer is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap for electrically connecting the first and second conductive layers in the trench to the source/drain region.
摘要翻译：提供一种形成耦合电容器和晶体管的方法。在半导体衬底中形成沟槽，然后通过用杂质掺杂的第一导电材料填充沟槽来形成杂质掺杂的第一导电区域。杂质掺杂的第一导电区域被回蚀刻到沟槽内的第一水平。然后在通过杂质掺杂的第一导电区域的蚀刻开口的沟槽部分的侧壁上形成绝缘层，并且通过用第二导电材料填充沟槽的其余部分形成第二导电区域。将绝缘层和第二导电区域回蚀刻到沟槽内的第二层，并且在通过绝缘层和第二导电区域的蚀刻打开的沟槽部分中形成非晶硅层。未掺杂的非晶硅层在沟槽内回蚀刻到第三级。然后将未掺杂的非晶硅层重结晶。杂质通过再结晶硅层从杂质掺杂的第一导电区向外延伸到半导体衬底。晶体管的源极/漏极区域形成为与沟槽和半导体衬底的表面的交点相邻。超扩散杂质和再结晶硅层构成用于将沟槽中的第一和第二导电层电连接到源极/漏极区域的掩埋带。

6. 发明授权

US5804499A Prevention of abnormal WSi.sub.x oxidation by in-situ amorphous silicon deposition 失效
标题翻译：通过原位非晶硅沉积防止异常WSix氧化
公开(公告)号：US5804499A
公开(公告)日：1998-09-08
申请号：US642294
申请日：1996-05-03
申请人： Christine Dehm , Reinhard J. Stengl , Hans-Joerg Timme
发明人： Christine Dehm , Reinhard J. Stengl , Hans-Joerg Timme
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/285
CPC分类号： H01L21/76838 , H01L21/28061 , H01L21/28247
摘要： A process which prevents abnormal WSi.sub.x oxidation during subsequent LPCVD insulator deposition and gate sidewall oxidation, uses an in-situ deposition of a thin amorphous silicon layer on top of the tungsten silicide as well as the deposition of an amorphous spacer after gate stack patterning, respectively.
摘要翻译：在随后的LPCVD绝缘体沉积和栅极侧壁氧化期间防止异常WSix氧化的过程分别使用硅化钨顶部上的薄非晶硅层的原位沉积以及栅极堆叠图案化之后的非晶间隔物的沉积。

7. 发明授权

US5792685A Three-dimensional device layout having a trench capacitor 失效
标题翻译：具有沟槽电容器的三维器件布局
公开(公告)号：US5792685A
公开(公告)日：1998-08-11
申请号：US667541
申请日：1996-06-21
申请人： Erwin Hammerl , Jack A. Mandelman , Bernhard Poschenrieder , Alvin P. Short , Radhika Srinivasan , Reinhard J. Stengl , Herbert L. Ho
发明人： Erwin Hammerl , Jack A. Mandelman , Bernhard Poschenrieder , Alvin P. Short , Radhika Srinivasan , Reinhard J. Stengl , Herbert L. Ho
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.
摘要翻译：公开了一种用于形成包括形成在第一装置上的第二装置的三维装置结构的方法。在第一装置上方形成具有单一晶体顶表面的层，以提供用于形成第二装置的有效区域的基座。

8. 发明授权

US5674769A Process for forming deep trench DRAMs with sub-groundrule gates 失效
标题翻译：用次基底栅形成深沟槽DRAM的工艺
公开(公告)号：US5674769A
公开(公告)日：1997-10-07
申请号：US665183
申请日：1996-06-14
申请人： Johann Alsmeier , Christine Dehm , Erwin Hammerl , Reinhard J. Stengl
发明人： Johann Alsmeier , Christine Dehm , Erwin Hammerl , Reinhard J. Stengl
IPC分类号： H01L29/41 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： A method of fabricating sub-GR gates in a deep trench DRAM cell. The method comprises depositing, removing, and selectively etching a plurality of layers which include sacrificial spacers, liners, masking, and resist layers of both semiconducting and non-semiconducting materials on a semiconductor substrate according to specific process flows designed to circumvent the problems associated with prior art sub-GR processes. The method represents an improvement on standard gate conductor processes and provides a device which achieves an up to now unachieved decoupling of channel doping and junction doping.
摘要翻译：在深沟槽DRAM单元中制造子GR栅极的方法。该方法包括在半导体衬底上沉积，去除和选择性地蚀刻包括半导体衬底上的半导体和非半导体材料的牺牲隔离物，衬垫，掩模和抗蚀剂层的多个层，所述特定工艺流程旨在规避与现有技术的子GR过程。该方法代表了对标准栅极导体工艺的改进，并且提供了实现通道掺杂和结掺杂的迄今未达成的去耦的器件。

9. 发明授权

US5663107A Global planarization using self aligned polishing or spacer technique and isotropic etch process 失效
标题翻译：使用自对准抛光或间隔技术的全局平面化和各向同性蚀刻工艺
公开(公告)号：US5663107A
公开(公告)日：1997-09-02
申请号：US362399
申请日：1994-12-22
申请人： Matthias L. Peschke , Reinhard J. Stengl
发明人： Matthias L. Peschke , Reinhard J. Stengl
IPC分类号： H01L21/31 , H01L21/304 , H01L21/3105 , H01L21/316 , H01L21/318 , H01L21/3205 , H01L21/82
CPC分类号： H01L21/31055
摘要： A method for globally planarizing an integrated circuit device wafer having a plurality of structures disposed on a surface thereof, the structures forming up and down features on the wafer's surface. The method involves depositing a fill layer over the surface of the wafer to cover the structures. Next, an etch mask layer is deposited over the fill layer. After the etch mask layer is fabricated, openings are formed in the etch mask layer to expose areas of the fill layer that are to be subsequently etched. This is accomplished in the first embodiment of the invention by creating self aligned openings in the etch mask layer using CMP if the gaps between the structures are only partially filled. If the gaps between the structures are completely filled, openings in the etch mask layer can be provided by patterning the etch mask layer using lithography and performing an optional spacer deposition and etching step as described in a second embodiment of the invention. In either case, the exposed areas of the fill layer are then etched to provide a second surface having up features that are substantially smaller than the up features originally defined on the surface of the wafer. In the final step of the method, the up features of the second surface are polished to provide a planarized wafer surface.
摘要翻译：一种用于全面平面化具有设置在其表面上的多个结构的集成电路器件晶片的方法，所述结构在晶片表面上形成上下特征。该方法包括在晶片的表面上沉积填充层以覆盖结构。接下来，在填充层上沉积蚀刻掩模层。在制造蚀刻掩模层之后，在蚀刻掩模层中形成开口以暴露待随后蚀刻的填充层的区域。这在本发明的第一实施例中通过如果结构之间的间隙仅被部分地填充而通过使用CMP在蚀刻掩模层中产生自对准的开口来实现。如果结构之间的间隙被完全填充，则可以通过使用光刻图案化蚀刻掩模层并且执行如本发明的第二实施例中所述的可选的间隔物沉积和蚀刻步骤来提供蚀刻掩模层中的开口。在任一情况下，然后蚀刻填充层的暴露区域以提供具有基本上小于原始限定在晶片表面上的特征的特征的第二表面。在该方法的最后步骤中，抛光第二表面的向上特征以提供平坦化的晶片表面。

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