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1. 发明授权

US06556618B1 Transmitter, receiver and method in a telecommunication system for generating PN sequences for a plurality of user channels 有权
标题翻译：用于生成用于多个用户信道的PN序列的电信系统中的发射机，接收机和方法
公开(公告)号：US06556618B1
公开(公告)日：2003-04-29
申请号：US09382795
申请日：1999-08-25
申请人： Gerd Mörsberger , Gian Huaman-Bollo , Helmut Leuschner
发明人： Gerd Mörsberger , Gian Huaman-Bollo , Helmut Leuschner
IPC分类号： H04B169
CPC分类号： H04J13/0022 , H04B1/707 , H04J13/10 , H04L1/20
摘要： In a telecommunication system where a plurality of user channels are processed in a time-slotted manner, a transmitter and receiver can perform bit error rate measurements for a plurality of user channels by only using one PN-generator (T-PN) and one state memory (ISM). Whenever the beginning of a new time-slot is detected, a last-stored phase state is read out from the state memory (ISM). When detecting the end of the respective time-slot, the phase state then present in the PN-generator (T-PN) is stored into the state memory (ISM) to be used for re-initialization of the PN-generator (T-PN) for the same time-slot in a succeeding frame. Thus, one PN-generator (T-PN) is enough for generating PN-sequences for a great number of user channels.
摘要翻译：在以时隙方式处理多个用户信道的电信系统中，发射机和接收机可以通过仅使用一个PN发生器（T-PN）和一个状态来对多个用户信道执行比特误码率测量记忆体（ISM）。每当检测到新的时隙的开始时，从状态存储器（ISM）中读出最后存储的相位状态。当检测到相应的时隙的结束时，存在于PN发生器（T-PN）中的相位状态被存储到状态存储器（ISM）中，以用于PN发生器（T- PN），用于在后续帧中相同的时隙。因此，一个PN发生器（T-PN）足以产生大量用户信道的PN序列。

2. 发明授权

US07437655B2 Apparatus and method for flexible data rate matching 有权
标题翻译：灵活数据速率匹配的装置和方法
公开(公告)号：US07437655B2
公开(公告)日：2008-10-14
申请号：US10500538
申请日：2002-09-18
申请人： Gerd Mörsberger , Stefan Schütz , Georg Spörlein
发明人： Gerd Mörsberger , Stefan Schütz , Georg Spörlein
IPC分类号： H03M13/03 , H04J3/22
CPC分类号： H04L1/0043 , H04L1/0069 , H04L1/0071 , H04L1/08
摘要： This invention relates to a flexible rate matching method, comprising the steps of: a) receiving a continuous stream of data items at a prespecified rate of a clock signal in a configurable data shift register; b) storing, for each data item stored in the data shirt register, an associated indication of validity in a configurable validity shift register and shifting the indications of validity at said prespecified rate; c) modifying the contents of the data shift register and the validity shift register through puncture/repetition operations so as to achieve a rate matching, and d) outputting valid data items at said prespecified rate using said indications of validity stored in the validity shift register. The invention also relates to a corresponding flexible rate matching apparatus as well as to a computer program product and a processor program product.
摘要翻译：本发明涉及一种灵活的速率匹配方法，包括以下步骤：a）以可配置数据移位寄存器中的时钟信号的预定速率接收数据项的连续流; b）对于存储在数据移位寄存器中的每个数据项存储可配置的有效性移位寄存器中的有效性的相关指示，并以所述预定速率移位有效性的指示; c）通过穿刺/重复操作来修改数据移位寄存器和有效移位寄存器的内容以便实现速率匹配，以及d）使用存储在有效移位寄存器中的所述有效性指示，以所述预定速率输出有效数据项。本发明还涉及相应的灵活速率匹配装置以及计算机程序产品和处理器程序产品。

3. 发明授权

US06651209B1 Parallel turbo coder implementation 有权
标题翻译：并行turbo编码器实现
公开(公告)号：US06651209B1
公开(公告)日：2003-11-18
申请号：US09660290
申请日：2000-09-12
申请人： Gerd Mörsberger , Georg Sporlein
发明人： Gerd Mörsberger , Georg Sporlein
IPC分类号： H03M1300
CPC分类号： H03M13/6561 , H03M13/235 , H03M13/2903 , H03M13/2957
摘要： A turbo coder block having a parallelization of degree n achieves increased processing speed. Each parallelized turbo coder block includes a first storage unit to store n samples of an input signal and a second storage unit to store n samples of at least one output signal of the parallelized turbo coding block. The parallelized turbo coder block further includes a bank of n delay units and is adapted to parallel process n samples of the input signal such that two delay units of the bank directly receive subsets of the n samples of the input signal, and an output signal of one delay unit is supplied to two delay units in the parallelized turbo coder block.
摘要翻译：具有等级n的并行化的turbo编码器块实现了增加的处理速度。每个并行化的turbo编码器块包括第一存储单元，用于存储输入信号的n个样本和第二存储单元，以存储并行化turbo编码块的至少一个输出信号的n个采样。并行化turbo编码器模块还包括一组n个延迟单元，并且适于并行处理输入信号的n个样本，使得存储体的两个延迟单元直接接收输入信号的n个采样的子集，并且输出信号一个延迟单元被提供给并行涡轮编码器块中的两个延迟单元。

4. 发明授权

US07961477B2 Housing comprising a liquid-tight electric bushing 有权
标题翻译：壳体包括液密电气套管
公开(公告)号：US07961477B2
公开(公告)日：2011-06-14
申请号：US10588556
申请日：2004-12-27
申请人： Josef Deuringer , Richard Eichhorn , Lars Lauer , Gerd Mörsberger , Paul Ponnath , Roland Rabe
发明人： Josef Deuringer , Richard Eichhorn , Lars Lauer , Gerd Mörsberger , Paul Ponnath , Roland Rabe
IPC分类号： H05K5/00
CPC分类号： H01R13/5202 , H01J2235/023 , H01R12/523 , H01R12/58 , Y10T29/49126 , Y10T29/49165
摘要： A housing comprising a liquid-tight electric bushing is provided. The housing comprises an opening and a printed circuit board comprising at least first and second layers. The first layer is a top side of the printed circuit board and spans the opening. A first contact element is disposed on the top side and in a blind bore through the first layer that extends to the second layer. The second layer is a conductor track in the interior of the printed circuit board.
摘要翻译：提供了一种包括液密电气套管的壳体。壳体包括开口和包括至少第一层和第二层的印刷电路板。第一层是印刷电路板的顶面并跨越开口。第一接触元件设置在顶侧和盲孔中，穿过延伸到第二层的第一层。第二层是印刷电路板内部的导体轨迹。

5. 发明授权

US07091889B2 Speed and memory optimized interleaving 有权
标题翻译：速度和内存优化交错
公开(公告)号：US07091889B2
公开(公告)日：2006-08-15
申请号：US10526519
申请日：2002-09-09
申请人： Ralf Kukla , Stefan Schütz , Georg Spörlein , Gerd Mörsberger
发明人： Ralf Kukla , Stefan Schütz , Georg Spörlein , Gerd Mörsberger
IPC分类号： H03M7/00
CPC分类号： H04L1/0071 , H03M13/271 , H03M13/2714 , H03M13/2764 , H03M13/2771 , H03M13/2957 , H03M13/635
摘要： This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting. according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the interleaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.
摘要翻译：本发明涉及一种用于根据交织方案将包含K个比特的输入序列交织到交错序列中的方法，包括以下步骤：（a）将输入序列存储在第一存储器装置中，（b）产生第一索引交错序列的N个后续位，其中1 m（F）N m（F）K，（c）转换。根据所述交织方案的逆，所述第一索引为指示所述交错序列的所述N个后续位存储在所述第一存储器装置中的位置的第二索引，以及（d）从所述第一存储器装置中的所述位置读出所述N个后续位所述第一存储器装置，从而产生所述交错序列的至少一部分。

6. 发明授权

US06560746B1 Parallel CRC generation circuit for generating a CRC code 失效
标题翻译：并行CRC生成电路，用于生成CRC码
公开(公告)号：US06560746B1
公开(公告)日：2003-05-06
申请号：US09382591
申请日：1999-08-25
申请人： Gerd Mörsberger
发明人： Gerd Mörsberger
IPC分类号： H03M1300
CPC分类号： H03M13/091 , H03M13/6575
摘要： The invention relates to a parallel CRC generation circuit comprising an input register means (I), an output register means (C), a number of XOR gates (XOR1-XORN) and a coupling means (CM) that feeds predetermined ones of the output lines (C0-CN−1) of the output register means (C) and output lines (I1-In) of the input register means (I) as inputs to the respective XOR gates. According to the invention a matrix representation of the state change based on the selected CRC polynomial is set up and evaluated, such that the coupling means (CM) only uses the minimum number of feedbacks of the output lines and feed-forwards of the output lines of the input register means (I). Thus, the parallel CRC calculation circuit according to the invention has no redundancy and uses only a minimum hardware amount.
摘要翻译：本发明涉及一种并行CRC生成电路，包括输入寄存器装置（I），输出寄存器装置（C），多个异或门（XOR1-XORN）和耦合装置（CM），其馈送预定的输出输出寄存器装置（C）的输出线（C0-CN-1）和输入寄存器装置（I）的输出线（I1-In）作为各个异或门的输入。根据本发明，建立并评估基于选择的CRC多项式的状态变化的矩阵表示，使得耦合装置（CM）仅使用输出线的反馈的最小数量和输出线的前馈的输入寄存器装置（I）。因此，根据本发明的并行CRC计算电路没有冗余并且仅使用最小硬件量。

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