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1. 发明授权

US07269149B2 Interleaving for mobile communications 有权
标题翻译：交错移动通信
公开(公告)号：US07269149B2
公开(公告)日：2007-09-11
申请号：US10528604
申请日：2002-09-24
申请人： Ralf Kukla , Gerd Morsberger , Georg Sporlein , Gerhard Goedert , Edmund Goetz
发明人： Ralf Kukla , Gerd Morsberger , Georg Sporlein , Gerhard Goedert , Edmund Goetz
IPC分类号： H04Q7/00
CPC分类号： H03M13/27 , H04L1/0045 , H04L1/0071
摘要： A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.
摘要翻译：一种用于处理数字通信系统中的比特序列的方法，包括以下步骤：（a）将所述比特序列的比特存储在由第一交织方案指示的存储器装置的位置处，（b）将输出比特位置转换成输入比特根据第二交织方案的倒数，（c）读出存储在与所述输入比特位置对应的所述存储装置的位置处的比特，从而产生根据所述第一和所述第二交织方案进行交织的交错序列，以及（d）根据进一步的物理处理步骤处理所述交错序列。或者，步骤（a）可以包括将所述输入比特序列的比特存储在存储装置中，并且步骤（b）可以包括根据第一交织方案的顺序应用的反向将输出比特位置转换成输入比特位置第二交织方案。

2. 发明授权

US06512757B1 Pipeline processing for data channels 有权
标题翻译：数据通道的管道处理
公开(公告)号：US06512757B1
公开(公告)日：2003-01-28
申请号：US09468903
申请日：1999-12-22
申请人： Michael Niegel , Ralf Kukla , Seyed-Hami Nourbakhsh
发明人： Michael Niegel , Ralf Kukla , Seyed-Hami Nourbakhsh
IPC分类号： H04B7216
CPC分类号： H04W52/04 , G06F15/8053
摘要： Method and apparatus for processing a plurality of data channels, e.g., of a CDMA telecommunications system, using a pipeline structure. The invention allows to process channels in an interleaved fashion, where each of a plurality of pipeline stages may access channel specific data using channel addresses transmitted via addressing means. In order to synchronize the transmission of processing results and addresses associated with the data channels, the addressing means comprises a plurality of delay units. With the invention power control and measurement operations for a plurality of channels may be facilitated.
摘要翻译：用于使用流水线结构处理例如CDMA电信系统的多个数据信道的方法和装置。本发明允许以交错方式处理信道，其中多个流水线级中的每一个可以使用经由寻址装置发送的信道地址来访问信道特定数据。为了同步处理结果的传输和与数据信道相关联的地址，寻址装置包括多个延迟单元。利用本发明，可以促进用于多个通道的功率控制和测量操作。

3. 发明授权

US06625136B1 Spreader for multiple data rates 有权
标题翻译： Spreader用于多种数据速率
公开(公告)号：US06625136B1
公开(公告)日：2003-09-23
申请号：US09353647
申请日：1999-07-15
申请人： Michael Niegel , Ralf Kukla , Seyed-Hami Nourbakhsh
发明人： Michael Niegel , Ralf Kukla , Seyed-Hami Nourbakhsh
IPC分类号： H04B7216
CPC分类号： H04J13/16
摘要： The present invention relates to spreading data of a plurality of digital communication channels having different data rates with code sequences having different lengths. The inventive circuit allows to use a single hardware unit for spreading communication channels having different data rates, e.g. in a CDMA telecommunications system. This is achieved by processing either a single symbol and a corresponding long code in appropriate storage means for a channel with a lowest rate or to process a plurality of symbols and corresponding shorter code sequences of communication channels having higher data rates. Thus, a joint chip rate after spreading is obtained using a single hardware structure.
摘要翻译：本发明涉及具有不同数据速率的多个数字通信信道的扩展数据与具有不同长度的码序列。本发明的电路允许使用单个硬件单元来扩展具有不同数据速率的通信信道，例如，在CDMA电信系统中。这通过在具有最低速率的信道的适当存储装置中处理单个符号和对应的长码来实现，或者处理具有较高数据速率的通信信道的多个符号和对应的较短代码序列。因此，使用单个硬件结构获得扩展后的联合码片速率。

4. 发明申请

US20060140142A1 Interleaving for mobile communications 有权
标题翻译：交错移动通信
公开(公告)号：US20060140142A1
公开(公告)日：2006-06-29
申请号：US10528604
申请日：2002-09-24
申请人： Ralf Kukla , Gerd Morsberger , Georg Sporlein , Gerhard Goedert , Edmund Goetz
发明人： Ralf Kukla , Gerd Morsberger , Georg Sporlein , Gerhard Goedert , Edmund Goetz
IPC分类号： H04Q7/00
CPC分类号： H03M13/27 , H04L1/0045 , H04L1/0071
摘要： A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.
摘要翻译：一种用于处理数字通信系统中的比特序列的方法，包括以下步骤：（a）将所述比特序列的比特存储在由第一交织方案指示的存储器装置的位置处，（b）将输出比特位置转换成输入比特根据第二交织方案的倒数，（c）读出存储在与所述输入比特位置对应的所述存储装置的位置处的比特，从而产生根据所述第一和所述第二交织方案进行交织的交错序列，以及（d）根据进一步的物理处理步骤处理所述交错序列。或者，步骤（a）可以包括将所述输入比特序列的比特存储在存储装置中，并且步骤（b）可以包括根据第一交织方案的顺序应用的反向将输出比特位置转换成输入比特位置第二交织方案。

5. 发明授权

US06735239B1 Sequence generator 有权
标题翻译：序列发生器
公开(公告)号：US06735239B1
公开(公告)日：2004-05-11
申请号：US09310068
申请日：1999-05-11
申请人： Michael Niegel , Ralf Kukla , Seyed-Hami Nourbakhsh
发明人： Michael Niegel , Ralf Kukla , Seyed-Hami Nourbakhsh
IPC分类号： H04B1707
CPC分类号： H04J13/10 , H03K3/84
摘要： A sequence generator for generating sequences of binary or discrete values may be flexibly adjusted to requirements. Shift register memory locations may be selected as feed-back locations for generating a feed-back signal. Further, shift register memory locations may be selected as feed-in locations for receiving the feed-back signal. A plurality of control memory locations store a control bit sequence for controlling the sequence generator. The sequence generator may be used as a longcode and/or shortcode generator in a CDMA-telecommunications system.
摘要翻译：用于产生二进制或离散值序列的序列发生器可以灵活地调整为要求。可以将移位寄存器存储器位置选择为用于产生反馈信号的反馈位置。此外，可以选择移位寄存器存储器位置作为用于接收反馈信号的馈入位置。多个控制存储器位置存储用于控制序列发生器的控制位序列。序列生成器可以用作CDMA电信系统中的长码和/或短码生成器。

6. 发明授权

US06633557B1 Combiner 有权
标题翻译：组合器
公开(公告)号：US06633557B1
公开(公告)日：2003-10-14
申请号：US09437237
申请日：1999-11-10
申请人： Michael Niegel , Ralf Kukla , Seyed-Hami Nourbakhsh
发明人： Michael Niegel , Ralf Kukla , Seyed-Hami Nourbakhsh
IPC分类号： H04B7216
CPC分类号： H04J13/00
摘要： Circuitry combines a plurality of digital communication channels in a telecommunication system with reduced hardware requirements. The circuitry accumulates samples of the input communication channels in a register using an adder. The bit width of the connection lines between the register and the adder may be selected considering the bit width and number of input communication channels, such that minimal bit widths are provided.
摘要翻译：电路将电信系统中的多个数字通信信道与硬件要求降低相结合。该电路使用加法器将寄存器中的输入通信信道的采样累加。考虑到位宽度和输入通信通道的数量，可以选择寄存器和加法器之间的连接线的位宽度，以便提供最小的位宽。

7. 发明授权

US07091889B2 Speed and memory optimized interleaving 有权
标题翻译：速度和内存优化交错
公开(公告)号：US07091889B2
公开(公告)日：2006-08-15
申请号：US10526519
申请日：2002-09-09
申请人： Ralf Kukla , Stefan Schütz , Georg Spörlein , Gerd Mörsberger
发明人： Ralf Kukla , Stefan Schütz , Georg Spörlein , Gerd Mörsberger
IPC分类号： H03M7/00
CPC分类号： H04L1/0071 , H03M13/271 , H03M13/2714 , H03M13/2764 , H03M13/2771 , H03M13/2957 , H03M13/635
摘要： This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting. according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the interleaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.
摘要翻译：本发明涉及一种用于根据交织方案将包含K个比特的输入序列交织到交错序列中的方法，包括以下步骤：（a）将输入序列存储在第一存储器装置中，（b）产生第一索引交错序列的N个后续位，其中1 m（F）N m（F）K，（c）转换。根据所述交织方案的逆，所述第一索引为指示所述交错序列的所述N个后续位存储在所述第一存储器装置中的位置的第二索引，以及（d）从所述第一存储器装置中的所述位置读出所述N个后续位所述第一存储器装置，从而产生所述交错序列的至少一部分。

8. 发明申请

US20050248473A1 Speed and memory optimised interleaving 有权
标题翻译：速度和内存优化交错
公开(公告)号：US20050248473A1
公开(公告)日：2005-11-10
申请号：US10526519
申请日：2002-09-09
申请人： Ralf Kukla , Stefan Schutz , Georg Sporlein , Gerd Morsberger
发明人： Ralf Kukla , Stefan Schutz , Georg Sporlein , Gerd Morsberger
IPC分类号： H03M13/27 , H03M13/29 , H04L1/00 , H03M7/00
CPC分类号： H04L1/0071 , H03M13/271 , H03M13/2714 , H03M13/2764 , H03M13/2771 , H03M13/2957 , H03M13/635
摘要： This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting, according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the inter-leaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.
摘要翻译：本发明涉及一种根据交织方案将包括K个比特的输入序列交织到交错序列中的方法，包括以下步骤：（a）将输入序列存储在第一存储器装置中，（b）产生第一索引其中1 m（F）N m（F）K，（c）根据所述交织方案的反向将所述第一索引转换为指示所述N个后续比特的位置的第二索引并且（d）从所述第一存储器装置中的所述位置读出所述N个后续位，从而产生所述交错序列的至少一部分。

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