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1. 发明授权

US07091889B2 Speed and memory optimized interleaving 有权
标题翻译：速度和内存优化交错
公开(公告)号：US07091889B2
公开(公告)日：2006-08-15
申请号：US10526519
申请日：2002-09-09
申请人： Ralf Kukla , Stefan Schütz , Georg Spörlein , Gerd Mörsberger
发明人： Ralf Kukla , Stefan Schütz , Georg Spörlein , Gerd Mörsberger
IPC分类号： H03M7/00
CPC分类号： H04L1/0071 , H03M13/271 , H03M13/2714 , H03M13/2764 , H03M13/2771 , H03M13/2957 , H03M13/635
摘要： This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting. according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the interleaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.
摘要翻译：本发明涉及一种用于根据交织方案将包含K个比特的输入序列交织到交错序列中的方法，包括以下步骤：（a）将输入序列存储在第一存储器装置中，（b）产生第一索引交错序列的N个后续位，其中1 m（F）N m（F）K，（c）转换。根据所述交织方案的逆，所述第一索引为指示所述交错序列的所述N个后续位存储在所述第一存储器装置中的位置的第二索引，以及（d）从所述第一存储器装置中的所述位置读出所述N个后续位所述第一存储器装置，从而产生所述交错序列的至少一部分。

2. 发明授权

US07437655B2 Apparatus and method for flexible data rate matching 有权
标题翻译：灵活数据速率匹配的装置和方法
公开(公告)号：US07437655B2
公开(公告)日：2008-10-14
申请号：US10500538
申请日：2002-09-18
申请人： Gerd Mörsberger , Stefan Schütz , Georg Spörlein
发明人： Gerd Mörsberger , Stefan Schütz , Georg Spörlein
IPC分类号： H03M13/03 , H04J3/22
CPC分类号： H04L1/0043 , H04L1/0069 , H04L1/0071 , H04L1/08
摘要： This invention relates to a flexible rate matching method, comprising the steps of: a) receiving a continuous stream of data items at a prespecified rate of a clock signal in a configurable data shift register; b) storing, for each data item stored in the data shirt register, an associated indication of validity in a configurable validity shift register and shifting the indications of validity at said prespecified rate; c) modifying the contents of the data shift register and the validity shift register through puncture/repetition operations so as to achieve a rate matching, and d) outputting valid data items at said prespecified rate using said indications of validity stored in the validity shift register. The invention also relates to a corresponding flexible rate matching apparatus as well as to a computer program product and a processor program product.
摘要翻译：本发明涉及一种灵活的速率匹配方法，包括以下步骤：a）以可配置数据移位寄存器中的时钟信号的预定速率接收数据项的连续流; b）对于存储在数据移位寄存器中的每个数据项存储可配置的有效性移位寄存器中的有效性的相关指示，并以所述预定速率移位有效性的指示; c）通过穿刺/重复操作来修改数据移位寄存器和有效移位寄存器的内容以便实现速率匹配，以及d）使用存储在有效移位寄存器中的所述有效性指示，以所述预定速率输出有效数据项。本发明还涉及相应的灵活速率匹配装置以及计算机程序产品和处理器程序产品。

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