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1. 发明授权

US06879046B2 Split barrier layer including nitrogen-containing portion and oxygen-containing portion 有权
标题翻译：分离阻挡层包括含氮部分和含氧部分
公开(公告)号：US06879046B2
公开(公告)日：2005-04-12
申请号：US10038371
申请日：2002-01-02
申请人： Gerald W Gibson, Jr. , Scott Jessen , Steven Alan Lytle , Kurt George Steiner , Susan Clay Vitkavage
发明人： Gerald W Gibson, Jr. , Scott Jessen , Steven Alan Lytle , Kurt George Steiner , Susan Clay Vitkavage
IPC分类号： H01L23/522 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L59/40
CPC分类号： H01L21/76835 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02315 , H01L21/02362 , H01L21/312 , H01L21/3146 , H01L21/31633 , H01L21/31695 , H01L21/76801 , H01L21/76808 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/31663 , H01L2924/00
摘要： A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide. The hardmask and etch-stop layer enable the formation of a dual-damascene opening in the film stack, and the film structure of the present invention precludes N—H base groups from diffusing from the low-k dielectric films and neutralizing acid catalysts in the photoresist used to define the dual damascene opening.
摘要翻译：分裂阻挡层使得铜互连线可以与低k电介质膜结合使用，方法是防止N-H基团扩散到光致抗蚀剂中，从而使光致抗蚀剂不可溶。分裂阻挡层设置在铜和低k电介质之间，并且包括与铜接触的含氮的无氧膜和与低k电介质膜接触的含氧无氮膜。含氮膜防止形成不期望的铜氧化物，并且含氧膜防止N-H基团扩散到低k电介质膜中。在示例性实施例中，含氧膜可以是氧掺杂碳化硅膜。在另一个实施例中，低k电介质膜的薄膜叠层包括蚀刻停止层和各自由氧掺杂的碳化硅形成的硬掩模。硬掩模和蚀刻停止层使得能够在膜堆叠中形成双镶嵌开口，并且本发明的膜结构排除了NH基团从所使用的光致抗蚀剂中的低k电介质膜和中和酸催化剂扩散定义双镶嵌开口。

2. 发明授权

US07068139B2 Inductor formed in an integrated circuit 有权
公开(公告)号：US07068139B2
公开(公告)日：2006-06-27
申请号：US10953475
申请日：2004-09-29
申请人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
发明人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
IPC分类号： H01F5/00
CPC分类号： H01L24/10 , H01F41/041 , H01L23/5227 , H01L24/13 , H01L27/08 , H01L28/10 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , Y10T29/4902 , H01L2924/00 , H01L2224/48
摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

3. 发明授权

US06548892B1 Low k dielectric insulator and method of forming semiconductor circuit structures 有权
标题翻译：低k电介质绝缘体和形成半导体电路结构的方法
公开(公告)号：US06548892B1
公开(公告)日：2003-04-15
申请号：US09653297
申请日：2000-08-31
申请人： Kurt George Steiner , Susan Clay Vitkavage
发明人： Kurt George Steiner , Susan Clay Vitkavage
IPC分类号： H01L2312
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02271 , H01L21/02304 , H01L21/31695 , H01L21/76829 , H01L21/76832 , H01L2924/0002 , H01L2924/00
摘要： A porous insulator material and method of manufacturing. The material comprises oxygen, silicon and hydrogen characterized by a density less than 2 g/cc. Alternately, the porous insulator material is characterized by a refractive index less than 1.45 for light at a wavelength between 633 nm and 673 nm, or by a Young's modulus less than 45 GPa. A method for manufacturing a semiconductor device includes providing a semiconductor layer with an upper surface for device formation and forming multiple levels of interconnect over the semiconductor layer, each level including a plurality of members. The members are electrically isolated from other members by decomposition of TEOS to form a porous layer between at least some of the members.
摘要翻译：多孔绝缘体材料及其制造方法。该材料包括氧，硅和氢，其特征在于密度小于2g / cc。或者，多孔绝缘体材料的特征在于对于在633nm和673nm之间的波长的光或者小于45GPa的杨氏模量，折射率小于1.45。一种制造半导体器件的方法包括：提供具有用于器件形成的上表面的半导体层，并在该半导体层上形成多层次的互连，每个级包括多个部件。这些构件通过TEOS的分解与其它构件电隔离，以在至少一些构件之间形成多孔层。

4. 发明授权

US07678639B2 Inductor formed in an integrated circuit 有权
标题翻译：集成电路中形成的电感器
公开(公告)号：US07678639B2
公开(公告)日：2010-03-16
申请号：US12340813
申请日：2008-12-22
申请人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
发明人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
IPC分类号： H01L21/8238
CPC分类号： H01L24/10 , H01F41/041 , H01L23/5227 , H01L24/13 , H01L27/08 , H01L28/10 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , Y10T29/4902 , H01L2924/00 , H01L2224/48
摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
摘要翻译：在集成电路内形成的电感器和形成电感器的方法。该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。在一个实施例中，铝线包括螺旋形状。根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。铝线和导电流道配合形成电感器。在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。形成电感器的方法包括形成铝导线并在导线上形成导电流道。

5. 发明授权

US07541238B2 Inductor formed in an integrated circuit 有权
标题翻译：集成电路中形成的电感器
公开(公告)号：US07541238B2
公开(公告)日：2009-06-02
申请号：US11414902
申请日：2006-05-01
申请人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
发明人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
IPC分类号： H01L21/8238
CPC分类号： H01L24/10 , H01F41/041 , H01L23/5227 , H01L24/13 , H01L27/08 , H01L28/10 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , Y10T29/4902 , H01L2924/00 , H01L2224/48
摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
摘要翻译：在集成电路内形成的电感器和形成电感器的方法。该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。在一个实施例中，铝线包括螺旋形状。根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。铝线和导电流道配合形成电感器。在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。形成电感器的方法包括形成铝导线并在导线上形成导电流道。

6. 发明申请

US20090100668A1 INDUCTOR FORMED IN AN INTEGRATED CIRCUIT 有权
标题翻译：在一体化电路中形成的电感器
公开(公告)号：US20090100668A1
公开(公告)日：2009-04-23
申请号：US12340813
申请日：2008-12-22
申请人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
发明人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
IPC分类号： H01F41/00
CPC分类号： H01L24/10 , H01F41/041 , H01L23/5227 , H01L24/13 , H01L27/08 , H01L28/10 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , Y10T29/4902 , H01L2924/00 , H01L2224/48
摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
摘要翻译：在集成电路内形成的电感器和形成电感器的方法。该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。在一个实施例中，铝线包括螺旋形状。根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。铝线和导电流道配合形成电感器。在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。形成电感器的方法包括形成铝导线并在导线上形成导电流道。

7. 发明授权

US07332775B2 Protruding spacers for self-aligned contacts 有权
标题翻译：用于自对准触点的突出间隔件
公开(公告)号：US07332775B2
公开(公告)日：2008-02-19
申请号：US11542864
申请日：2006-10-04
申请人： Kurt George Steiner , Gerald W. Gibson, Jr. , Eduardo Jose Quinones
发明人： Kurt George Steiner , Gerald W. Gibson, Jr. , Eduardo Jose Quinones
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L21/76897 , H01L29/665 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.
摘要翻译：在栅电极结构的顶表面上方突出的突出间隔物在用于形成自对准接触的蚀刻工艺期间提供增强的栅电极的暴露电阻。可以使用非晶碳牺牲层作为图案化栅极电极结构的顶层来形成突出间隔物。电介质间隔物与栅电极结构一起形成，包括在牺牲无定形碳层的旁边。电介质隔离层基本上延伸到无定形碳层的顶部。然后去除无定形碳层，使得剩余的栅极结构包括具有在剩余栅极结构的顶表面上方突出的突出部分的电介质间隔物。可以在栅极结构上形成氮化物层。这种结构防止了在形成自对准触点时栅电极的暴露，并且一旦接触开口被填充就会短路。

8. 发明授权

US07126198B2 Protruding spacers for self-aligned contacts 有权
标题翻译：用于自对准触点的突出间隔件
公开(公告)号：US07126198B2
公开(公告)日：2006-10-24
申请号：US10234354
申请日：2002-09-03
申请人： Kurt George Steiner , Gerald W. Gibson, Jr. , Eduardo Jose Quinones
发明人： Kurt George Steiner , Gerald W. Gibson, Jr. , Eduardo Jose Quinones
IPC分类号： H01L31/119 , H01L23/52 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/76897 , H01L29/665 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.
摘要翻译：在栅电极结构的顶表面上方突出的突出间隔物在用于形成自对准接触的蚀刻工艺期间提供增强的栅电极的暴露电阻。可以使用非晶碳牺牲层作为图案化栅极电极结构的顶层来形成突出间隔物。电介质间隔物与栅电极结构一起形成，包括在牺牲无定形碳层的旁边。电介质隔离层基本上延伸到无定形碳层的顶部。然后去除无定形碳层，使得剩余的栅极结构包括具有在剩余栅极结构的顶表面上方突出的突出部分的电介质间隔物。可以在栅极结构上形成氮化物层。这种结构防止了在形成自对准触点时栅电极的暴露，并且一旦接触开口被填充就会短路。

9. 发明授权

US5891784A Transistor fabrication method 失效
标题翻译：晶体管制造方法
公开(公告)号：US5891784A
公开(公告)日：1999-04-06
申请号：US430084
申请日：1995-04-27
申请人： Wan Yee Cheung , Sailesh Chittipeddi , Chong-Cheng Fu , Taeho Kook , Avinoam Kornblit , Steven Alan Lytle , Kurt George Steiner , Tungsheng Yang
发明人： Wan Yee Cheung , Sailesh Chittipeddi , Chong-Cheng Fu , Taeho Kook , Avinoam Kornblit , Steven Alan Lytle , Kurt George Steiner , Tungsheng Yang
IPC分类号： H01L21/027 , H01L21/336 , H01L21/331
CPC分类号： H01L21/0276 , H01L29/665 , H01L29/66545 , H01L29/66575 , H01L29/6659 , Y10S438/952
摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.
摘要翻译：公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。抗反射涂层有助于防止反光门开槽。可以形成各种硅化和非硅化的结构。

10. 发明授权

US07067419B2 Mask layer and dual damascene interconnect structure in a semiconductor device 失效
公开(公告)号：US07067419B2
公开(公告)日：2006-06-27
申请号：US10721126
申请日：2003-11-25
申请人： Robert Y S Huang , Scott Jessen , Subramanian Karthikeyan , Joshua Jia Li , Isaiah O. Oladeji , Kurt George Steiner , Joseph Ashley Taylor
发明人： Robert Y S Huang , Scott Jessen , Subramanian Karthikeyan , Joshua Jia Li , Isaiah O. Oladeji , Kurt George Steiner , Joseph Ashley Taylor
IPC分类号： H01L21/467
CPC分类号： H01L21/76811 , H01L21/76813
摘要： A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.

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