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1. 发明授权

US5649135A Parallel processing system and method using surrogate instructions 失效
标题翻译：并行处理系统和使用代理指令的方法
公开(公告)号：US5649135A
公开(公告)日：1997-07-15
申请号：US373128
申请日：1995-01-17
申请人： Gerald G. Pechanek , Clair John Glossner , Larry D. Larsen , Stamatis Vassiliadis
发明人： Gerald G. Pechanek , Clair John Glossner , Larry D. Larsen , Stamatis Vassiliadis
IPC分类号： G06F9/318 , G06F9/38 , G06F15/16 , G06F15/80 , G06F9/355
CPC分类号： G06F9/3885 , G06F17/142 , G06F9/30072 , G06F9/30181
摘要： A parallel processing system and method is disclosed, which provides an improved instruction distribution mechanism for a parallel processing array. The invention broadcasts a basic instruction to each of a plurality of processor elements. Each processor element decodes the same instruction by combining it with a unique offset value stored in each respective processor element, to produce a derived instruction that is unique to the processor element. A first type of basic instruction results in the processor element performing a logical or control operation. A second type of basic instruction results in the generation of a pointer address. The pointer address has a unique address value because it results from combining the basic instruction with the unique offset value stored at the processor element. The pointer address is used to access an alternative instruction from an alternative instruction storage, for execution in the processor element. The alternative instruction is a very long instruction word, whose length is, for example, an integral multiple of the length of the basic instruction and contains much more information than can be represented by the basic instruction. A very long instruction word such as this is useful for providing parallel control of a plurality of primitive execution units that reside within the processor element. In this manner, a high degree of flexibility and versatility is attained in the operation of processor elements of a parallel processing array.
摘要翻译：公开了一种并行处理系统和方法，其提供了用于并行处理阵列的改进的指令分配机制。本发明向多个处理器元件中的每一个广播基本指令。每个处理器元件通过将其与存储在每个相应处理器元件中的唯一偏移值组合来解码相同的指令，以产生对于处理器元件唯一的导出指令。第一类基本指令导致处理器元件执行逻辑或控制操作。第二种类型的基本指令导致生成指针地址。指针地址具有唯一的地址值，因为它是将基本指令与存储在处理器元件中的唯一偏移值组合而产生的。指针地址用于从替代指令存储器访问替代指令，以在处理器元件中执行。替代指令是非常长的指令字，其长度例如是基本指令的长度的整数倍，并且包含比基本指令可以表示的更多的信息。诸如此类的非常长的指令字对于提供驻留在处理器元件内的多个基本执行单元的并行控制是有用的。以这种方式，在并行处理阵列的处理器元件的操作中获得高度的灵活性和多功能性。

2. 发明授权

US5659785A Array processor communication architecture with broadcast processor instructions 失效
标题翻译：具有广播处理器指令的阵列处理器通信架构
公开(公告)号：US5659785A
公开(公告)日：1997-08-19
申请号：US386384
申请日：1995-02-10
申请人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
发明人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80
CPC分类号： G06F15/17381
摘要： A plurality of processor elements (PEs) are connected in a duster by a common instruction bus to a sequencing control unit with its associated instruction memory. Each PE has data buses connected to at least its four nearest PE neighbors, referred to as its North, South, East and West PE neighbors. Each PE also has a general purpose register file containing several operand registers. A common instruction is fetched from the instruction memory by the sequencing control unit and broadcast over the instruction bus to each PE in the cluster. The instruction includes an upcode value that controls the arithmetic or logical operation performed by an execution unit in the PE on one or more operands in the register file. A switch is included in each PE to interconnect it with a first PE neighbor as the destination to which the result from the execution unit is sent. The broadcast instruction includes a destination field that controls the switch in the PE, to dynamically select the destination neighbor PE to which the result is sent. Further, the broadcast instruction includes a target field that controls the switch in the PE, to dynamically select the operand register in the register file of the PE, to which another result received from another neighbor PE in the cluster is stored. In this manner, the instruction broadcast to all the PEs in the cluster, dynamically controls the communication of operands and results between the PEs in the cluster, in a single instruction, multiple data processor array.
摘要翻译：多个处理器元件（PE）通过公共指令总线连接到除尘器中，其具有与其相关联的指令存储器的排序控制单元。每个PE都有数据总线连接到至少其四个最近的PE邻居，称为其北，南，东和西PE邻居。每个PE还有一个包含多个操作数寄存器的通用寄存器文件。通过排序控制单元从指令存储器取出通用指令，并通过指令总线广播到集群中的每个PE。该指令包括一个上限值，其控制由PE中的执行单元在寄存器文件中的一个或多个操作数上执行的算术或逻辑操作。每个PE中包括一个交换机，将其与第一个PE邻居进行互连，作为发送执行单元的结果的目的地。广播指令包括控制PE中的交换机的目的地字段，动态地选择发送结果的目的地邻居PE。此外，广播指令包括控制PE中的交换机的目标字段，动态地选择PE的寄存器文件中的操作数寄存器，存储从群集中的另一个邻居PE接收到的另一结果。以这种方式，向集群中的所有PE广播的指令在单个指令，多数据处理器阵列中动态地控制集群中的PE之间的操作数和结果的通信。

3. 发明授权

US6128720A Distributed processing array with component processors performing customized interpretation of instructions 失效
标题翻译：具有组件处理器的分布式处理阵列执行指令的定制解释
公开(公告)号：US6128720A
公开(公告)日：2000-10-03
申请号：US838803
申请日：1997-04-10
申请人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
发明人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
IPC分类号： G06F9/318 , G06F9/38 , G06F15/80 , G06F15/16
CPC分类号： G06F9/30185 , G06F15/8007 , G06F9/30189 , G06F9/3885 , G06F9/3887
摘要： A multi-processor array organization is dynamically configured by the inclusion of a configuration topology field in instructions broadcast to the processors in the array. Each of the processors in the array is capable of performing a customized data selection and storage, instruction execution, and result destination selection, by uniquely interpreting a broadcast instruction by using the identity of the processor executing the instruction. In this manner, processing elements in a large multi-processing array can be dynamically reconfigured and have their operations customized for each processor using broadcast instructions.
摘要翻译：通过在阵列中的处理器广播的指令中包括配置拓扑字段来动态配置多处理器阵列组织。通过使用执行指令的处理器的身份来唯一地解释广播指令，阵列中的每个处理器能够执行定制的数据选择和存储，指令执行和结果目的地选择。以这种方式，可以动态地重新配置大型多处理阵列中的处理元件，并使用广播指令为每个处理器定制其操作。

4. 发明授权

US5682491A Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier 失效
标题翻译：使用从指令标签和处理器标识符导出的掩码值，由解码指令控制的处理器之间的结果的选择性处理和路由选择
公开(公告)号：US5682491A
公开(公告)日：1997-10-28
申请号：US366140
申请日：1994-12-29
申请人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis , Daniel H. McCabe
发明人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis , Daniel H. McCabe
IPC分类号： G06F9/30 , G06F9/318 , G06F15/80 , G06F15/16
CPC分类号： G06F9/3885 , G06F15/8007 , G06F9/3012 , G06F9/30145 , G06F9/30185 , G06F9/30189 , G06F9/3887 , G06F9/3889
摘要： An array processor topology reconfiguration system and method enables processor elements in an array to dynamically reconfigure their mutual interconnection for the exchange of arithmetic results between the processors. Each processor element includes an interconnection switch which is controlled by an instruction decoder in the processor. Instructions are broadcast to all of the processors in the array. The instructions are uniquely interpreted at each respective processor in the array, depending upon the processor identity. The interpretation of the commonly broadcast instruction is uniquely performed at each processor by combining the processor identity for the executing processor, with a value in the instruction. The resulting control signals from the instruction decoder to the interconnection switch, provides for a customized linkage between the executing processor and other processors in the array.
摘要翻译：阵列处理器拓扑重构系统和方法使阵列中的处理器元件能够动态地重新配置它们的相互互连，以便在处理器之间交换算术结果。每个处理器元件包括由处理器中的指令解码器控制的互连开关。指令将广播到阵列中的所有处理器。取决于处理器标识，指令在阵列中的每个相应处理器处被唯一地解释。通过将执行处理器的处理器标识与指令中的值组合，在每个处理器处唯一地执行对广播指令的解释。从指令解码器到互连交换机的结果控制信号提供执行处理器与阵列中的其他处理器之间的定制连接。

5. 发明授权

US5509106A Triangular scalable neural array processor 失效
标题翻译：三角缩放神经阵列处理器
公开(公告)号：US5509106A
公开(公告)日：1996-04-16
申请号：US231853
申请日：1994-04-22
申请人： Gerald G. Pechanek , Stamatis Vassiliadis
发明人： Gerald G. Pechanek , Stamatis Vassiliadis
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/063 , G06N3/10 , G06N99/00
CPC分类号： G06N3/063 , G06N3/10
摘要： A triangular scalable neural array processor unit for use in a neural network and having multipliers, communicating adder trees, sigmoid generators, and a reverse feedback loop for communicating the output of a sigmoid generator back to input multipliers of selected neurons.
摘要翻译：一种用于神经网络并具有乘法器，通信加法器树，S形发生器和反向反馈回路的三角形可扩展神经阵列处理器单元，用于将S型输出端的输出反馈到选定神经元的输入乘法器。

6. 发明授权

US4924422A Method and apparatus for modified carry-save determination of arithmetic/logic zero results 失效
标题翻译：用于修改进位保存确定算术/逻辑零结果的方法和装置
公开(公告)号：US4924422A
公开(公告)日：1990-05-08
申请号：US157500
申请日：1988-02-17
申请人： Stamatis Vassiliadis , Michael Putrino , Ann E. Huffman , Brice J. Feal , Gerald G. Pechanek
发明人： Stamatis Vassiliadis , Michael Putrino , Ann E. Huffman , Brice J. Feal , Gerald G. Pechanek
IPC分类号： G06F7/02 , G06F7/50 , G06F7/507 , G06F7/508 , G06F7/57 , G06F9/32
CPC分类号： G06F7/57 , G06F7/026 , G06F7/505 , G06F9/30094 , G06F7/49905
摘要： The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.

7. 发明授权

US5617512A Triangular scalable neural array processor 失效
标题翻译：三角缩放神经阵列处理器
公开(公告)号：US5617512A
公开(公告)日：1997-04-01
申请号：US459191
申请日：1995-06-02
申请人： Gerald G. Pechanek , Stamatis Vassiliadis
发明人： Gerald G. Pechanek , Stamatis Vassiliadis
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/063 , G06N3/10 , G06N99/00
CPC分类号： G06N3/063 , G06N3/10
摘要： A neural array processor computing structure with a plurality of processing units which have orthogonal sets of neurons and communicating adder trees which provide a reverse communication path. Each processing unit has a weight storage unit. The processing units are arranged so that they are connected to the weight storage units in symmetric pairs. General processing cells share communication paths so that a reduced number of communicating adder trees is used.
摘要翻译：具有多个处理单元的神经阵列处理器计算结构，所述多个处理单元具有提供反向通信路径的正交神经元集合和通信加法器树。每个处理单元具有一个重量存储单元。处理单元被布置成使得它们以对称的对连接到重量存储单元。通用处理单元共享通信路径，从而使用减少数量的通信加法器树。

8. 发明授权

US5613044A Learning machine synapse processor system apparatus 失效
标题翻译：学习机突触处理器系统设备
公开(公告)号：US5613044A
公开(公告)日：1997-03-18
申请号：US459199
申请日：1995-06-02
申请人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
发明人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
IPC分类号： G06F15/18
CPC分类号： G06N3/063
摘要： A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage units, receive instructions and data, and execute instructions. The N neuron structure should contain communicating adder trees, neuron activation function units, and an arrangement for communicating both instructions, data, and the outputs of neuron activation function units back to the input synapse processing units by means of the communicating adder trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 synapse processing units, each associated with a connection weight in the N neural network to be emulated, placed in the form of a N by N matrix that has been folded along the diagonal and made up of diagonal cells and general cells. Diagonal cells, each utilizing a single synapse processing unit, are associated with the diagonal connection weights of the folded N by N connection weight matrix and general cells, each of which has two synapse processing units merged together, and which are associated with the symmetric connection weights of the folded N by N connection weight matrix. The back-propagation learning algorithm is first discussed followed by a presentation of the learning machine synapse processor architecture. An example implementation of the back-propagation learning algorithm is then presented. This is followed by a Boltzmann like machine example and data parallel examples mapped onto the architecture.
摘要翻译：一种具有用于装置的突触处理元件的神经元结构的神经突触处理器装置。我们喜欢的装置将具有具有包含指令和数据存储单元，接收指令和数据以及执行指令的突触处理单元的N个神经元结构。 N神经元结构应包含通信加法器树，神经激活功能单元和用于通过通信加法器树将神经元激活功能单元的指令，数据和输出传送回输入突触处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选结构包含N 2个突触处理单元，每个N突触处理单元与N个仿真网络中的连接权重相关联，以N×N矩阵的形式放置，该矩阵已经沿对角线折叠并由对角线单元和通用单元组成。每个使用单个突触处理单元的对角线单元与折叠的N乘N连接权重矩阵和通用单元的对角连接权重相关联，每个单元具有合并在一起的两个突触处理单元，并且与对称连接相关联折叠N乘以N连接权重矩阵的权重。首先讨论反向传播学习算法，然后介绍学习机器突触处理器架构。然后呈现反向传播学习算法的示例实现。接下来是一个Boltzmann的机器示例，并将数据并行示例映射到架构上。

9. 发明授权

US5517596A Learning machine synapse processor system apparatus 失效
标题翻译：学习机突触处理器系统设备
公开(公告)号：US5517596A
公开(公告)日：1996-05-14
申请号：US161839
申请日：1993-12-01
申请人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
发明人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
IPC分类号： G06F15/18
CPC分类号： G06N3/063
摘要： A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage units, receive instructions and data, and execute instructions. The N neuron structure should contain communicating adder trees, neuron activation function units, and an arrangement for communicating both instructions, data, and the outputs of neuron activation function units back to the input synapse processing units by means of the communicating adder trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 synapse processing units, each associated with a connection weight in the N neural network to be emulated, placed in the form of a N by N matrix that has been folded along the diagonal and made up of diagonal cells and general cells. Diagonal cells, each utilizing a single synapse processing unit, are associated with the diagonal connection weights of the folded N by N connection weight matrix and general cells, each of which has two synapse processing units merged together, and which are associated with the symmetric connection weights of the folded N by N connection weight matrix. The back-propagation learning algorithm is first discussed followed by a presentation of the learning machine synapse processor architecture. An example implementation of the back-propagation learning algorithm is then presented. This is followed by a Boltzmann like machine example and data parallel examples mapped onto the architecture.
摘要翻译：一种具有用于装置的突触处理元件的神经元结构的神经突触处理器装置。我们喜欢的装置将具有具有包含指令和数据存储单元，接收指令和数据以及执行指令的突触处理单元的N个神经元结构。 N神经元结构应包含通信加法器树，神经激活功能单元和用于通过通信加法器树将神经元激活功能单元的指令，数据和输出传送回输入突触处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选结构包含N 2个突触处理单元，每个N突触处理单元与N个仿真网络中的连接权重相关联，以N×N矩阵的形式放置，该矩阵已经沿对角线折叠并由对角线单元和通用单元组成。每个使用单个突触处理单元的对角线单元与折叠的N乘N连接权重矩阵和通用单元的对角连接权重相关联，每个单元具有合并在一起的两个突触处理单元，并且与对称连接相关联折叠N乘以N连接权重矩阵的权重。首先讨论反向传播学习算法，然后介绍学习机器突触处理器架构。然后呈现反向传播学习算法的示例实现。接下来是一个Boltzmann的机器示例，并将数据并行示例映射到架构上。

10. 发明授权

US5065339A Orthogonal row-column neural processor 失效
标题翻译：正交圆柱神经处理器
公开(公告)号：US5065339A
公开(公告)日：1991-11-12
申请号：US526866
申请日：1990-05-22
申请人： Stamatis Vassiliadis , Gerald G. Pechanek
发明人： Stamatis Vassiliadis , Gerald G. Pechanek
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/063 , G06N3/10 , G06N99/00
CPC分类号： G06N3/063 , G06N3/10
摘要： The neural computing paradigm is characterized as a dynamic and highly parallel computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture called SNAP which uses a unique intercommunication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP's packaging and expansion capabilities are addressed, demonstrating SNAP's scalability to larger networks. Each neuron generating a neuron value from a selected set of input function elements and communicating said neuron value back to said set of input function elements. The total connectivity of each neuron to all neurons is accomplished by an orthogonal row-column relationship of neurons where a given multiplier element operates during a first cycle as a row element within an input function to a column neuron, and during a second cycle as a column element within an input function to a row neuron.

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