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    • 6. 发明申请
    • Error correction compensating ones or zeros string suppression
    • 纠错补偿或零字符串抑制
    • US20060026483A1
    • 2006-02-02
    • US10910433
    • 2004-08-02
    • Christopher Read
    • Christopher Read
    • G06F11/00G06F11/30G08C25/00H03M13/00H04L1/00
    • H04L1/0041
    • An error correction compensating ones or zeros string suppression system and method for use in a digital transmission system is herein disclosed. In digital transmission systems utilizing error control coding (ECC)/forward error correction (FEC) to reduce the number of bit errors in a bit stream, long strings of ones and zeros are easily suppressed by detecting a prohibited length of ones or zeros, and flipping a bit in the string of ones or zeros. This method and system removes the violation of the ones or zeros bit string requirement by flipping a bit in the string, while the receiving side utilizes the error correction capability of the ECC/FEC to correct the inverted bit.
    • 本文公开了一种用于数字传输系统的纠错补偿补偿或零字符串抑制系统和方法。 在利用误差控制编码(ECC)/前向纠错(FEC)的数字传输系统中,为了减少比特流中的比特错误的数量,通过检测1或0的禁止长度容易地抑制长串的1和0, 翻转一个字符串的一个或零。 该方法和系统通过翻转字符串中的位来消除对1或0位的比特串要求的违反,而接收侧利用ECC / FEC的纠错能力来校正反相位。
    • 8. 发明授权
    • System and method for effectively protecting electronic content information
    • 有效保护电子内容信息的系统和方法
    • US08300818B2
    • 2012-10-30
    • US11711381
    • 2007-02-27
    • Christopher Read
    • Christopher Read
    • G06F3/14G06F13/10
    • G06F21/10
    • A system and method for effectively protecting electronic content information includes a channel setup module that coordinates a channel setup procedure to create a secure communications channel between a content drive and a display module. A source DRM module transmits a special content key from the content drive to the display module over the secure communications channel. A content playback module then initiates a content playback procedure for utilizing the electronic content. The source DRM module responsively encrypts the electronic content with the content key. The channel setup module and the content playback module are unable to access or utilize the content key. A destination DRM module then receives the electronic content over the secure communications channel and utilizes the content key to decrypt the electronic content.
    • 用于有效保护电子内容信息的系统和方法包括:信道建立模块,其协调信道建立过程以在内容驱动器和显示模块之间建立安全通信信道。 源DRM模块通过安全通信信道将特殊内容密钥从内容驱动器发送到显示模块。 内容回放模块然后启动用于利用电子内容的内容重放过程。 源DRM模块用内容密钥对电子内容进行响应式加密。 频道设置模块和内容播放模块不能访问或利用内容密钥。 目的地DRM模块然后通过安全通信信道接收电子内容,并利用内容密钥对电子内容进行解密。
    • 9. 发明申请
    • System and method for effectively protecting electronic content information
    • 有效保护电子内容信息的系统和方法
    • US20080205656A1
    • 2008-08-28
    • US11711381
    • 2007-02-27
    • Christopher Read
    • Christopher Read
    • H04L9/00
    • G06F21/10
    • A system and method for effectively protecting electronic content information includes a channel setup module that coordinates a channel setup procedure to create a secure communications channel between a content drive and a display module. A source DRM module transmits a special content key from the content drive to the display module over the secure communications channel. A content playback module then initiates a content playback procedure for utilizing the electronic content. The source DRM module responsively encrypts the electronic content with the content key. The channel setup module and the content playback module are unable to access or utilize the content key. A destination DRM module then receives the electronic content over the secure communications channel and utilizes the content key to decrypt the electronic content.
    • 用于有效保护电子内容信息的系统和方法包括:信道建立模块,其协调信道建立过程以在内容驱动器和显示模块之间建立安全通信信道。 源DRM模块通过安全通信信道将特殊内容密钥从内容驱动器发送到显示模块。 内容回放模块然后启动用于利用电子内容的内容重放过程。 源DRM模块用内容密钥对电子内容进行响应式加密。 频道设置模块和内容播放模块不能访问或利用内容密钥。 目的地DRM模块然后通过安全通信信道接收电子内容,并利用内容密钥对电子内容进行解密。
    • 10. 发明申请
    • Long Instruction Word Controlling Plural Independent Processor Operations
    • US20080077771A1
    • 2008-03-27
    • US11930652
    • 2007-10-31
    • Karl GuttagChristopher ReadKeith Balmer
    • Karl GuttagChristopher ReadKeith Balmer
    • G06F9/30
    • G06F7/53G06F7/57G06F9/30014G06F9/30032G06F9/30036G06F9/30145G06F9/30167G06F9/3851G06F9/3853G06F9/3867G06F9/3885G06F2207/382
    • This invention is a data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and a data transfer section. These instruction sections are independent and may include differing options. In the preferred embodiment, each instruction is 64 bits. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit (110) includes a multiplication unit (220) and an arithmetic logic unit (230). The data unit (110) may include a barrel rotator (235) for one input of the arithmetic logic unit (230). The rotated data may be stored in the first destination register instead of the multiply result. The address unit (120) operations according to the data transfer operation field. This could be a load, a store or a register to register move. Operations may be conditional based upon conditions stored in a status register (210). The status register (210) is set by a prior output of the arithmetic logic unit (230) and the instruction may specify some of the status bits protect from change. The address unit (120) preferably includes a plurality of base address registers (611), a full adder (615) and a left shifter (614). The full adder (615) may add an index as scaled by the left shifter to the base address or subtract the scaled index from the base address. The full adder (615) output may update the base address register (611), either before supply of the address or following supply of the address. The index may be recalled from an index register (612) or an immediate value. In the preferred embodiment of this invention, the data unit (110) including the data registers (200), the multiplication unit (220) and the arithmetic logic unit (230), the address unit (120) and the instruction decode logic (250, 660) are embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.