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1. 发明授权

US08865497B2 Planar cavity MEMS and related structures, methods of manufacture and design structures 有权
标题翻译：平面腔MEMS及相关结构，制造方法和设计结构
公开(公告)号：US08865497B2
公开(公告)日：2014-10-21
申请号：US12973422
申请日：2010-12-20
申请人： George A. Dunbar, III , Zhong-Xiang He , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper
发明人： George A. Dunbar, III , Zhong-Xiang He , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper
IPC分类号： H01L29/84 , B81C1/00 , B81B3/00 , G06F17/50 , H01H57/00
CPC分类号： B81B3/0072 , B81B3/0021 , B81B2201/01 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81C1/0015 , B81C1/00365 , B81C1/00476 , B81C1/00619 , B81C1/00626 , B81C1/00666 , B81C2201/0109 , B81C2201/013 , B81C2201/0167 , B81C2201/017 , B81C2203/0136 , B81C2203/0172 , G06F17/5068 , G06F17/5072 , H01H1/0036 , H01H57/00 , H01H59/0009 , H01H2057/006 , H01L41/1136 , H01L2924/0002 , Y10S438/937 , Y10T29/42 , Y10T29/435 , Y10T29/49002 , Y10T29/49105 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/5313 , H01L2924/00
摘要： A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition.
摘要翻译：形成至少一个微机电系统（MEMS）的方法包括在基板上形成下布线层。该方法还包括从下布线层形成多条分立布线。该方法还包括在多个离散导线上形成电极束。形成电极束和多个离散导线中的至少一个形成有最小化后续硅沉积中的小丘和三点的布局。

2. 发明授权

US09406472B2 Planar cavity MEMS and related structures, methods of manufacture and design structures 有权
标题翻译：平面腔MEMS及相关结构，制造方法和设计结构
公开(公告)号：US09406472B2
公开(公告)日：2016-08-02
申请号：US12974854
申请日：2010-12-21
申请人： Dinh Dang , Thai Doan , George A. Dunbar, III , Zhong-Xiang He , Russell T. Herrin , Christopher V. Jahnes , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , John G. Twombly , Eric J. White
发明人： Dinh Dang , Thai Doan , George A. Dunbar, III , Zhong-Xiang He , Russell T. Herrin , Christopher V. Jahnes , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , John G. Twombly , Eric J. White
IPC分类号： B81C1/00 , H01H59/00 , H01L21/768 , H01L41/113 , H01H57/00 , B81B3/00 , G06F17/50 , H01H1/00
CPC分类号： B81B3/0072 , B81B3/0021 , B81B2201/01 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81C1/0015 , B81C1/00365 , B81C1/00476 , B81C1/00619 , B81C1/00626 , B81C1/00666 , B81C2201/0109 , B81C2201/013 , B81C2201/0167 , B81C2201/017 , B81C2203/0136 , B81C2203/0172 , G06F17/5068 , G06F17/5072 , H01H1/0036 , H01H57/00 , H01H59/0009 , H01H2057/006 , H01L41/1136 , H01L2924/0002 , Y10S438/937 , Y10T29/42 , Y10T29/435 , Y10T29/49002 , Y10T29/49105 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/5313 , H01L2924/00
摘要： Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.
摘要翻译：提供了平面腔微机电系统（MEMS）结构，制造方法和设计结构。该方法包括使用反向镶嵌工艺形成具有平面表面的至少一个微机电系统（MEMS）空腔。

3. 发明授权

US08791545B2 Interconnect structures and design structures for a radiofrequency integrated circuit 有权
标题翻译：射频集成电路的互连结构和设计结构
公开(公告)号：US08791545B2
公开(公告)日：2014-07-29
申请号：US13560446
申请日：2012-07-27
申请人： Timothy J. Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
发明人： Timothy J. Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译：包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计，制造或测试诸如射频集成电路的集成电路。电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

4. 发明申请

US20120070979A1 METHOD OF ELECTROLYTIC PLATING AND SEMICONDUCTOR DEVICE FABRICATION 有权
标题翻译：电解镀层和半导体器件制造方法
公开(公告)号：US20120070979A1
公开(公告)日：2012-03-22
申请号：US12887737
申请日：2010-09-22
申请人： Felix P. Anderson , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Felix P. Anderson , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L21/768 , C25D5/12 , C25D5/14 , H01L21/02
CPC分类号： H01L21/7684 , C25D3/38 , C25D5/10 , C25D5/12 , H01L21/2885 , H01L21/76877
摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.
摘要翻译：本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。

5. 发明授权

US07915158B2 Method for forming an on-chip high frequency electro-static discharge device 有权
标题翻译：用于形成片上高频静电放电装置的方法
公开(公告)号：US07915158B2
公开(公告)日：2011-03-29
申请号：US12144071
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/3148 , H01L21/318 , H01L21/3185 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided. The wafer includes a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer. The more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer. The at least one of the misaligned vias forms a narrow gap with another misaligned via. A cavity trench is formed through the second dielectric layer between the narrow gap that separates the misaligned vias.
摘要翻译：描述形成片上高频静电放电装置的方法。在一个实施例中，提供具有多金属层布线的晶片。该晶片包括：第一电介质层，其中形成有多于一个电极;第二电介质层，设置在第一电介质层上，其中形成有多于一个电极，多个通孔将第一介电层中的多于一个的电极连接到在第二介电层中分别有一个以上的电极。多于一个通孔与第一介电层和第二介电层中的多于一个的电极不对准预定量。至少一个不对齐的通孔与另一个不对齐的通孔形成了狭窄的间隙。在分隔未对准的通孔的窄间隙之间通过第二介电层形成腔沟槽。

6. 发明申请

US20090316313A1 DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
标题翻译：片上高频电子放电装置的设计结构
公开(公告)号：US20090316313A1
公开(公告)日：2009-12-24
申请号：US12144084
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封以为所述集成电路提供静电放电保护。

7. 发明授权

US07494912B2 Terminal pad structures and methods of fabricating same 有权
标题翻译：端子焊盘结构及其制造方法
公开(公告)号：US07494912B2
公开(公告)日：2009-02-24
申请号：US11953927
申请日：2007-12-11
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

8. 发明申请

US20080173981A1 INTEGRATED CIRCUIT (IC) CHIP WITH ONE OR MORE VERTICAL PLATE CAPACITORS AND METHOD OF MAKING THE CAPACITORS 审中-公开
标题翻译：具有一个或多个垂直板电容器的集成电路（IC）芯片和制造电容器的方法
公开(公告)号：US20080173981A1
公开(公告)日：2008-07-24
申请号：US11624712
申请日：2007-01-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L28/91 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at least one upper plate layer (e.g., dual damascene copper) above, connected to and substantially identical with the base plate pattern. A vertical pair of capacitor plates are formed by the plate layer and base plate. Capacitor dielectric between the vertical pair of capacitor plates is, at least in part, a high-k dielectric.
摘要翻译：具有一个或多个垂直板电容器的集成电路（IC）芯片，每个垂直板电容器连接到IC芯片上的电路和制造芯片电容器的方法。垂直板电容器在电路层上形成有底板图案（例如，镶嵌铜），以及与基板图案连接并基本相同的至少一个上板层（例如双镶嵌铜）。一对电容器板由板层和底板形成。垂直对电容器板之间的电容电介质至少部分地是高k电介质。

9. 发明授权

US07382055B2 Integrated thin-film resistor with direct contact 有权
标题翻译：集成薄膜电阻直接接触
公开(公告)号：US07382055B2
公开(公告)日：2008-06-03
申请号：US11846595
申请日：2007-08-29
申请人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
发明人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
IPC分类号： H01L29/40
CPC分类号： H01L27/016
摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
摘要翻译：适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

10. 发明授权

US08842412B2 Tapered via and MIM capacitor 有权
公开(公告)号：US08842412B2
公开(公告)日：2014-09-23
申请号：US14176460
申请日：2014-02-10
申请人： James S. Dunn , Zhong-Xiang He , Anthony K. Stamper
发明人： James S. Dunn , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01G4/30 , H01L49/02
CPC分类号： H01L28/40 , H01G4/228 , H01G4/33
摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

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