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1. 发明申请

US20120070979A1 METHOD OF ELECTROLYTIC PLATING AND SEMICONDUCTOR DEVICE FABRICATION 有权
标题翻译：电解镀层和半导体器件制造方法
公开(公告)号：US20120070979A1
公开(公告)日：2012-03-22
申请号：US12887737
申请日：2010-09-22
申请人： Felix P. Anderson , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Felix P. Anderson , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L21/768 , C25D5/12 , C25D5/14 , H01L21/02
CPC分类号： H01L21/7684 , C25D3/38 , C25D5/10 , C25D5/12 , H01L21/2885 , H01L21/76877
摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.
摘要翻译：本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。

2. 发明授权

US08518817B2 Method of electrolytic plating and semiconductor device fabrication 有权
标题翻译：电解电镀和半导体器件制造方法
公开(公告)号：US08518817B2
公开(公告)日：2013-08-27
申请号：US12887737
申请日：2010-09-22
申请人： Felix P. Anderson , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Felix P. Anderson , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , C25D3/38 , C25D5/10 , C25D5/12 , H01L21/2885 , H01L21/76877
摘要： The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.
摘要翻译：本公开一般涉及半导体器件制造，更具体地涉及用于半导体器件制造中的电镀方法。电镀方法包括：将处理后的基板浸入电解镀液中以在工艺衬底上形成第一金属层; 然后对所述工艺衬底上的衬垫进行第一化学机械抛光，然后将所述工艺衬底浸入所述电解电镀溶液中，以在所述第一金属层和所述衬垫上形成第二金属层; 以及对所述衬垫执行第二化学机械抛光。

3. 发明授权

US08604898B2 Vertical integrated circuit switches, design structure and methods of fabricating same 有权
标题翻译：垂直集成电路开关，设计结构及其制造方法
公开(公告)号：US08604898B2
公开(公告)日：2013-12-10
申请号：US12426561
申请日：2009-04-20
申请人： Felix P. Anderson , Edward C. Cooney, III , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Edward C. Cooney, III , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01L2924/0002 , H01L2924/00
摘要： Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.
摘要翻译：本文提供垂直集成MEMS开关，制造这种垂直开关的设计结构和方法。制造MEMS开关的方法包括在晶片中形成至少两个垂直延伸的通孔，并用金属填充至少两个垂直延伸的通孔以形成至少两个垂直延伸的导线。该方法还包括从底侧打开晶片中的空隙，使得垂直延伸的线中的至少一个可在空隙内移动。

4. 发明授权

US08569091B2 Integrated circuit switches, design structure and methods of fabricating the same 有权
标题翻译：集成电路开关，设计结构及其制造方法
公开(公告)号：US08569091B2
公开(公告)日：2013-10-29
申请号：US12548697
申请日：2009-08-27
申请人： Felix P. Anderson , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B81C1/0015 , B81B3/0018 , B81B2201/014 , B81C1/00333 , B81C2203/0136 , B81C2203/0145 , G06F17/5068 , H01L21/302
摘要： Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further includes stripping the sacrificial material through at least one opening formed on the at least one tab which is on the side of the switching device, and sealing the at least one opening with a capping material.
摘要翻译：提供集成的MEMS开关，设计结构和制造这种开关的方法。该方法包括在嵌入在牺牲材料中的开关装置的侧面上形成牺牲材料的至少一个突片。该方法还包括通过形成在开关装置侧面上的至少一个突片上的至少一个开口剥离牺牲材料，并用封盖材料密封至少一个开口。

5. 发明授权

US08921975B2 System and method for forming aluminum fuse for compatibility with copper BEOL interconnect scheme 有权
标题翻译：用于形成铝保险丝的系统和方法，用于与铜BEOL互连方案兼容
公开(公告)号：US08921975B2
公开(公告)日：2014-12-30
申请号：US13488870
申请日：2012-06-05
申请人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L21/76892 , H01L21/76838 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.
摘要翻译：一种半导体熔丝器件和一种制造熔丝器件的方法，该熔丝器件包括最后的金属互连层，其包括至少两个分立的金属导体，沉积在最后的金属互连层和至少两个分立的金属导体上的层间电介质层，连接至少两个分立的金属导体的线铝保险丝，以及铝保险丝上方的保险丝开口。

6. 发明申请

US20100263998A1 VERTICAL INTEGRATED CIRCUIT SWITCHES, DESIGN STRUCTURE AND METHODS OF FABRICATING SAME 有权
标题翻译：垂直集成电路开关，设计结构及其制作方法
公开(公告)号：US20100263998A1
公开(公告)日：2010-10-21
申请号：US12426561
申请日：2009-04-20
申请人： Felix P. Anderson , Edward C. Cooney, III , Thomas L. Mcdevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Edward C. Cooney, III , Thomas L. Mcdevitt , Anthony K. Stamper
IPC分类号： H01H59/00 , H01L21/50 , G06F17/50 , H01L21/3213
CPC分类号： H01H59/0009 , H01L2924/0002 , H01L2924/00
摘要： Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.
摘要翻译：本文提供垂直集成MEMS开关，制造这种垂直开关的设计结构和方法。制造MEMS开关的方法包括在晶片中形成至少两个垂直延伸的通孔，并用金属填充至少两个垂直延伸的通孔以形成至少两个垂直延伸的导线。该方法还包括从底侧打开晶片中的空隙，使得垂直延伸的线中的至少一个可在空隙内移动。

7. 发明申请

US20100032829A1 STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于改善半导体器件中的焊接保护连接的结构和方法
公开(公告)号：US20100032829A1
公开(公告)日：2010-02-11
申请号：US12187646
申请日：2008-08-07
申请人： Felix P. Anderson , William Cote , Daniel C. Edelstein , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , William Cote , Daniel C. Edelstein , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/13 , H01L21/3105 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L23/53238 , H01L23/53295 , H01L24/11 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2221/1036 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05647 , H01L2224/05666 , H01L2224/13022 , H01L2224/13027 , H01L2224/13099 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/45147 , H01L2224/48847 , H01L2924/00011 , H01L2924/01005 , H01L2924/01014 , H01L2924/01018 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/19042 , H01L2924/00014 , H01L2924/00 , H01L2924/01006
摘要： Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.
摘要翻译：具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。该结构包括在至少一部分没有氟边界层的电介质层中形成的沟槽。该结构还包括在沟槽中的铜线，其至少其底部与沟槽的非氟化物边界层接触。无铅焊料凸块与铜线电接触。

8. 发明申请

US20110127673A1 WIRING STRUCTURE AND METHOD 审中-公开
标题翻译：接线结构和方法
公开(公告)号：US20110127673A1
公开(公告)日：2011-06-02
申请号：US12628481
申请日：2009-12-01
申请人： Felix P. Anderson , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is an improved integrated circuit wiring structure configured to prevent migration of wiring metal ions (e.g., copper (Cu+) ions in the case of a copper interconnect scheme) onto the surface of an interlayer dielectric material at an interface between the interlayer dielectric material and an insulating cap layer. Specifically, the top surfaces of wires and the top surface of a dielectric layer within which the wires sit are not co-planar. Thus, the interfaces between the wires and an insulating cap layer and between the dielectric layer and the same insulating cap layer are also not co-planar. Such a configuration physically prevents migration of wiring metal ions from the top surface of the wires onto the top surface of the dielectric layer at the interface between the dielectric layer and cap layer and, thereby prevents time dependent dielectric breakdown (TDDB) and eventual device failure. Also disclosed herein are embodiments of a method of a forming such an integrated circuit wiring structure.
摘要翻译：公开了一种改进的集成电路布线结构，其被配置为防止布线金属离子（例如在铜互连方案的情况下的铜（Cu +）离子）迁移到层间电介质材料的表面上，在层间电介质材料和绝缘盖层。具体地，电线的顶表面和电线所在的电介质层的顶表面不是共面的。因此，电线和绝缘帽层之间以及电介质层和相同绝缘帽层之间的界面也不是共面的。这种配置物理上防止布线金属离子从电介质顶表面在介电层和盖层之间的界面处迁移到电介质层的顶表面上，从而防止时间依赖的介质击穿（TDDB）和最终的器件故障。本文还公开了形成这种集成电路布线结构的方法的实施例。

9. 发明申请

US20090288869A1 CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT 有权
标题翻译：降低集成电路中高场密度区域的CURVILINEAR接线结构
公开(公告)号：US20090288869A1
公开(公告)日：2009-11-26
申请号：US12427775
申请日：2009-04-22
申请人： Felix P. Anderson , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H05K1/02 , H01R43/16
CPC分类号： H01L23/5283 , H01G4/232 , H01G4/306 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10T29/49204 , H01L2924/00
摘要： A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure.
摘要翻译：公开了一种用于减小集成电路中的高场强的区域的方法。在一个实施例中，该方法包括在集成电路的第一互连层中形成第一曲线布线结构。可以在集成电路的第二互连层中形成第二曲线布线结构，使得第一和第二曲线布线结构基本上垂直对齐。然后可以将第一曲线性布线结构电连接到第二曲线布线结构。

10. 发明申请

US20130320488A1 SYSTEM AND METHOD FOR FORMING ALUMINUM FUSE FOR COMPATIBILITY WITH COPPER BEOL INTERCONNECT SCHEME 有权
标题翻译：用于形成铝熔丝的系统和方法与铜球互连方案的兼容性
公开(公告)号：US20130320488A1
公开(公告)日：2013-12-05
申请号：US13488870
申请日：2012-06-05
申请人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L21/76892 , H01L21/76838 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.
摘要翻译：一种半导体熔丝器件和一种制造熔丝器件的方法，该熔丝器件包括最后的金属互连层，其包括至少两个分立的金属导体，沉积在最后的金属互连层和至少两个分立的金属导体上的层间电介质层，连接至少两个分立的金属导体的线铝保险丝，以及铝保险丝上方的保险丝开口。

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