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1. 发明授权

US07382055B2 Integrated thin-film resistor with direct contact 有权
标题翻译：集成薄膜电阻直接接触
公开(公告)号：US07382055B2
公开(公告)日：2008-06-03
申请号：US11846595
申请日：2007-08-29
申请人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
发明人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
IPC分类号： H01L29/40
CPC分类号： H01L27/016
摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
摘要翻译：适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

2. 发明授权

US07303972B2 Integrated thin-film resistor with direct contact 失效
标题翻译：集成薄膜电阻直接接触
公开(公告)号：US07303972B2
公开(公告)日：2007-12-04
申请号：US11275611
申请日：2006-01-19
申请人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
发明人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L27/016
摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
摘要翻译：适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

3. 发明授权

US07494748B2 Method for correction of defects in lithography masks 失效
标题翻译：光刻掩模中缺陷校正方法
公开(公告)号：US07494748B2
公开(公告)日：2009-02-24
申请号：US10904308
申请日：2004-11-03
申请人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
IPC分类号： G03F1/00
CPC分类号： G03F1/72 , G03F1/70
摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.
摘要翻译：用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。

4. 发明授权

US07224063B2 Dual-damascene metallization interconnection 有权
标题翻译：双镶嵌金属化互连
公开(公告)号：US07224063B2
公开(公告)日：2007-05-29
申请号：US09871883
申请日：2001-06-01
申请人： Birendra N. Agarwala , Eric M. Coker , Anthony Correale, Jr. , Hazara S. Rathore , Timothy D. Sullivan , Richard A. Wachnik
发明人： Birendra N. Agarwala , Eric M. Coker , Anthony Correale, Jr. , Hazara S. Rathore , Timothy D. Sullivan , Richard A. Wachnik
IPC分类号： H01L23/52
CPC分类号： H01L21/76852 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.
摘要翻译：一种互连结构，包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下层导线的侧面和底部上的下导电衬垫; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

5. 发明授权

US06760901B2 Trough adjusted optical proximity correction for vias 有权
标题翻译：通孔调整后的光学邻近校正
公开(公告)号：US06760901B2
公开(公告)日：2004-07-06
申请号：US10121153
申请日：2002-04-11
申请人： Bette L. Bergman Reuter , Eric M. Coker , William C. Leipold
发明人： Bette L. Bergman Reuter , Eric M. Coker , William C. Leipold
IPC分类号： G06F1750
CPC分类号： H01L21/76816 , G03F1/36 , G03F7/0035 , H01L21/76807 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior processing. The vias are classified into one of two groups, coincident vias which have an edge coincident with an edge of the trough, and noncoincident vias which do not have an edge coincident with an edge of the trough, by analyzing the via and trough designs. Any coincident via is marked as valid for an optical proximity correction (OPC). Any noncoincident via is marked invalid for OPC. OPC is then performed to the via level. Only vias marked as valid for OPC will keep the correction. All other vias will keep their original design size. Alternatively, coincident vias can be simply treated differently from noncoincident vias. For instance, coincident vias can be subjected to an aggressive OPC correction, while noncoincident vias are subjected to a less aggressive OPC correction.
摘要翻译：考虑到通过先前处理产生的晶片上的形貌的通孔的槽调节光学邻近校正。通过分析通孔和槽设计，将通孔分为两组中的一组，具有与槽的边缘一致的边缘的重合通孔和不具有与槽的边缘重合的边缘的非重合通路。任何符合通孔的标记对于光学邻近校正（OPC）都是有效的。对于OPC，任何非紧凑通道都被标记为无效。然后将OPC执行到通孔级。只有通过OPC标记为有效的通孔才能保持校正。所有其他通孔将保持原有的设计尺寸。或者，重合的通孔可以简单地被处理与非重合通路不同。例如，重合的通孔可以进行积极的OPC校正，而非重要的通孔受到较不激进的OPC校正。

6. 发明授权

US07470613B2 Dual damascene multi-level metallization 有权
标题翻译：双镶嵌多层金属化
公开(公告)号：US07470613B2
公开(公告)日：2008-12-30
申请号：US11619748
申请日：2007-01-04
申请人： Birendra N. Agarwala , Eric M. Coker , Anthony Correale, Jr. , Hazara S. Rathore , Timothy D. Sullivan , Richard A. Wachnik
发明人： Birendra N. Agarwala , Eric M. Coker , Anthony Correale, Jr. , Hazara S. Rathore , Timothy D. Sullivan , Richard A. Wachnik
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.
摘要翻译：一种用于形成互连结构的方法，所述互连结构包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下导电衬垫在侧面和底部的下层电线; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

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