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1. 发明授权

US07151060B2 Device and method for thermally treating semiconductor wafers 有权
公开(公告)号：US07151060B2
公开(公告)日：2006-12-19
申请号：US10524871
申请日：2003-07-25
申请人： Georg Roters , Steffen Frigge , Sing Pin Tay , Yao Zhi Hu , Regina Hayn , Jens-Uwe Sachse , Erwin Schoer , Wilhelm Kegel
发明人： Georg Roters , Steffen Frigge , Sing Pin Tay , Yao Zhi Hu , Regina Hayn , Jens-Uwe Sachse , Erwin Schoer , Wilhelm Kegel
IPC分类号： H01L21/324 , H01L21/477 , H01L21/42 , H01L21/26
CPC分类号： H01L21/67115 , H01L21/28247 , H01L21/32105
摘要： A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatment chamber receiving the substrate, with at least one wall part located adjacent to the radiation sources and which is substantially transparent for the radiation of said radiation source; and at least one cover plate between the substrate and the wall part of the treatment chamber located adjacent to the radiation sources, the dimensions of said cover plate being selected such that it fully covers the transparent wall part of the treatment chamber in relation to the substrate in order to prevent material, comprising a metal, metal oxide or metal hydroxide such as tungsten, tungsten oxide or tungsten hydroxide, from said substrate from becoming deposited on or evaporating onto the transparent wall part of the treatment chamber.

2. 发明申请

US20060105584A1 Device and method for thermally treating semiconductor wafers 有权
标题翻译：用于热处理半导体晶片的装置和方法
公开(公告)号：US20060105584A1
公开(公告)日：2006-05-18
申请号：US10524871
申请日：2003-07-25
申请人： Georg Roters , Steffen Frigge , Sing Tay , Yao Zhi Hu , Regina Hayn , Jens-Uwe Sachse , Erwin Schoer , Wilhelm Kegel
发明人： Georg Roters , Steffen Frigge , Sing Tay , Yao Zhi Hu , Regina Hayn , Jens-Uwe Sachse , Erwin Schoer , Wilhelm Kegel
IPC分类号： H01L21/324
CPC分类号： H01L21/67115 , H01L21/28247 , H01L21/32105
摘要： A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatment chamber receiving the substrate, with at least one wall part located adjacent to the radiation sources and which is substantially transparent for the radiation of said radiation source; and at least one cover plate between the substrate and the wall part of the treatment chamber located adjacent to the radiation sources, the dimensions of said cover plate being selected such that it fully covers the transparent wall part of the treatment chamber in relation to the substrate in order to prevent material, comprising a metal, metal oxide or metal hydroxide such as tungsten, tungsten oxide or tungsten hydroxide, from said substrate from becoming deposited on or evaporating onto the transparent wall part of the treatment chamber.
摘要翻译：一种用于热处理半导体晶片的装置，其具有至少一个待氧化的硅层和不被氧化的金属层，优选钨层。本发明的装置包括：至少一个辐射源; 接收衬底的处理室，其中至少一个壁部分位于辐射源附近，并且对于所述辐射源的辐射基本上是透明的; 以及至少一个覆盖板，位于基板与位于辐射源附近的处理室的壁部分之间，所述盖板的尺寸被选择为使得其相对于基板完全覆盖处理室的透明壁部分为了防止包含来自所述衬底的金属，金属氧化物或金属氢氧化物如钨，氧化钨或氢氧化钨的材料沉积在或蒸发到处理室的透明壁部分上。

3. 发明授权

US07094637B2 Method for minimizing the vapor deposition of tungsten oxide during the selective side wall oxidation of tungsten-silicon gates 有权
标题翻译：在钨硅栅极的选择性侧壁氧化期间最小化氧化钨的气相沉积的方法
公开(公告)号：US07094637B2
公开(公告)日：2006-08-22
申请号：US10694593
申请日：2003-10-27
申请人： Olaf Storbeck , Wilhelm Kegel , Jens-Uwe Sachse , Michael Stadtmüller , Regina Hayn , Erwin Schoer , Georg Roters , Steffen Frigge
发明人： Olaf Storbeck , Wilhelm Kegel , Jens-Uwe Sachse , Michael Stadtmüller , Regina Hayn , Erwin Schoer , Georg Roters , Steffen Frigge
IPC分类号： H01L21/337
CPC分类号： H01L21/32105 , H01L21/28061
摘要： During a selective oxidation of gate structures that includes a polycrystalline silicon layer and a tungsten layer, which is known per se, a vapor deposition of tungsten oxide is prevented or at least greatly reduced by a special process. The gate structure is acted on by a hydrogen-containing, nonaqueous inert gas before and, if appropriate, after a treatment step with a hydrogen/water mixture.
摘要翻译：在包括本身已知的多晶硅层和钨层的栅极结构的选择性氧化期间，通过特殊工艺防止或至少大大降低了氧化钨的气相沉积。栅极结构在氢/水混合物的处理步骤之前和（如果合适的话）之后由含氢非水惰性气体起作用。

4. 发明申请

US20060223267A1 Method of production of charge-trapping memory devices 审中-公开
标题翻译：电荷俘获存储器件的生产方法
公开(公告)号：US20060223267A1
公开(公告)日：2006-10-05
申请号：US11095925
申请日：2005-03-31
申请人： Stefan Machill , Christoph Ludwig , Jan-Malte Schley , Gunther Wein , Jens-Uwe Sachse , Mathias Krause , Mark Isler , Joachim Deppe
发明人： Stefan Machill , Christoph Ludwig , Jan-Malte Schley , Gunther Wein , Jens-Uwe Sachse , Mathias Krause , Mark Isler , Joachim Deppe
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/40117
摘要： The surfaces of wordline stacks and intermediate areas of a main substrate surface are covered with an oxynitride liner. Either sidewall spacers of BPSG are formed or a further liner of nitride is deposited and spacers of oxide are formed. These spacers are used in a peripheral area of addressing circuitry to implant doped source/drain regions. The oxynitride reduces the stress between the nitride and the semiconductor material and prevents charge carriers from penetrating out of a memory layer of nitride into the liner.
摘要翻译：主衬底表面的字线堆叠和中间区域的表面被氧氮化物衬垫覆盖。形成BPSG的侧壁间隔物，或者沉积另外的氮化物衬垫，并形成氧化物的间隔物。这些间隔物用于寻址电路的外围区域以注入掺杂的源极/漏极区域。氧氮化物降低了氮化物和半导体材料之间的应力，并且防止电荷载流子从氮化物的存储层渗透到衬里中。

5. 发明申请

US20060065922A1 Semiconductor memory with vertical charge-trapping memory cells and fabrication 审中-公开
标题翻译：具有垂直电荷捕获存储单元和制造的半导体存储器
公开(公告)号：US20060065922A1
公开(公告)日：2006-03-30
申请号：US11272637
申请日：2005-11-14
申请人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
发明人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L29/40117 , H01L29/66833
摘要： A semiconductor device is formed by forming a plurality of trenches in a semiconductor body. The trenches alternate between active trenches and isolation trenches with the isolation trenches being deeper than the active trenches. The semiconductor body is doped so that a top surface of the semiconductor body adjacent each active trench and a floor of each active trench is doped. Memory cell components are formed in each active trench. The memory cell components include a gate electrode and a charge-trapping layer disposed between the gate electrode and a sidewall of the trench. The charge-trapping layer includes a memory layer disposed between first and second limiting layers. Bitlines are formed over the semiconductor body and electrically coupled doped regions adjacent to the top surface of the semiconductor body adjacent the active trenches. Bitline contacts are coupled to the bitlines.
摘要翻译：半导体器件通过在半导体本体中形成多个沟槽而形成。沟槽在有源沟槽和隔离沟槽之间交替，隔离沟槽比有源沟槽更深。半导体本体被掺杂，使得与每个有源沟槽相邻的半导体本体的顶表面和每个有源沟槽的底板被掺杂。在每个有源沟槽中形成存储单元元件。存储单元部件包括设置在栅电极和沟槽的侧壁之间的栅电极和电荷捕获层。电荷捕获层包括设置在第一和第二限制层之间的存储层。位线形成在半导体主体上并与邻近有源沟槽的半导体本体的顶表面相邻的电耦合掺杂区。位线触点耦合到位线。

6. 发明授权

US06992348B2 Semiconductor memory with vertical charge-trapping memory cells and fabrication 失效
标题翻译：具有垂直电荷捕获存储单元和制造的半导体存储器
公开(公告)号：US06992348B2
公开(公告)日：2006-01-31
申请号：US10741970
申请日：2003-12-19
申请人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
发明人： Christoph Kleint , Joachim Deppe , Christoph Ludwig , Jens-Uwe Sachse
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L29/66833
摘要： Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.
摘要翻译：在存储单元场之外，在顶位线上提供位线触点，并且在下位线上提供额外的位线触点，并且各自以导电方式连接到为布线提供的金属化层。用于高位线的位线触点和用于低位线的附加位线触点形成在存储器单元场的相对侧上，并且隔离沟槽的部分存在于附加位线触点之间。

7. 发明授权

US07411837B2 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权
标题翻译：用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件
公开(公告)号：US07411837B2
公开(公告)日：2008-08-12
申请号：US11600425
申请日：2006-11-16
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Pablo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Pablo Mikalo
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译：提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域，其中信息被存储为有效参数的差异。

8. 发明申请

US20060267078A1 CHARGE-TRAPPING MEMORY DEVICE 失效
标题翻译：充电跟踪存储器件
公开(公告)号：US20060267078A1
公开(公告)日：2006-11-30
申请号：US11141254
申请日：2005-05-31
申请人： Ricardo Mikalo , Erwin Schroer , Gunther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Kleint
发明人： Ricardo Mikalo , Erwin Schroer , Gunther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Kleint
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.
摘要翻译：氧化区域布置在半导体材料的衬底和氮化物衬垫之间，其覆盖存储单元阵列的字线堆叠和衬底的中间区域，并且被提供以将氮化物衬垫与衬底和存储器层序列分离的电介质材料，用于电荷捕获。氮化物衬垫在形成用于外围区域的侧壁间隔物中用作蚀刻停止层，以产生寻址电路的晶体管的源极/漏极结。

9. 发明授权

US07015095B2 Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate 失效
标题翻译：一种制造具有电荷捕获存储单元和半导体衬底的半导体存储器的方法
公开(公告)号：US07015095B2
公开(公告)日：2006-03-21
申请号：US10856414
申请日：2004-05-27
申请人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
发明人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.
摘要翻译：导电材料被引入到字线（2）之间的间隙中，并且使用掩模（6）部分地移除，使得导电材料的残留部分（7）在每种情况下填充相关间隙的一部分并产生与源/漏区（15）的电接触。对于导电材料的另外部分，可以形成用于制造工艺的对准标记。

10. 发明申请

US20050195650A1 Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权
标题翻译：用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件
公开(公告)号：US20050195650A1
公开(公告)日：2005-09-08
申请号：US11072694
申请日：2005-03-04
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region (2) that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译：提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域（2），其中信息被存储为有效参数的差异。

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