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1. 发明授权

US06759874B2 Electronic circuit with a driver circuit 有权
标题翻译：具有驱动电路的电子电路
公开(公告)号：US06759874B2
公开(公告)日：2004-07-06
申请号：US10253001
申请日：2002-09-23
申请人： Georg Braun , Helmut Kandolf
发明人： Georg Braun , Helmut Kandolf
IPC分类号： H03K19094
CPC分类号： H03K19/0005
摘要： An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward resistance between a first supply voltage terminal and the signal line, and a second switching device with a second forward resistance between a second supply voltage terminal and the signal line. A control circuit is provided to generate a first and a second control signal to control the first and second switching devices in a first operating mode such that, depending on the signal which is to be driven, either the first switching device or the second switching device is through-connected. In a second operating mode, the first switching device and the second switching device are essentially through-connected with the aid of the first and second control signals so that the first and second forward resistances together form a terminating resistance.
摘要翻译：电子电路具有将信号驱动到信号线上的驱动电路。驱动器电路包括第一开关器件，其具有在第一电源电压端子和信号线之间的第一正向电阻，以及在第二电源电压端子和信号线之间具有第二正向电阻的第二开关器件。提供控制电路以产生第一和第二控制信号，以在第一操作模式下控制第一和第二开关装置，使得根据待驱动的信号，第一开关装置或第二开关装置是通过连接。在第二操作模式中，第一开关器件和第二开关器件借助于第一和第二控制信号基本上被连接，使得第一和第二正向电阻一起形成终止电阻。

2. 发明授权

US06459631B2 Configuration for implementing redundancy for a memory chip 有权
公开(公告)号：US06459631B2
公开(公告)日：2002-10-01
申请号：US09907783
申请日：2001-07-18
申请人： Helmut Fischer , Helmut Kandolf , Stefan Lammers
发明人： Helmut Fischer , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/812 , G11C29/844
摘要： The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy predecoder so that predecoded addresses can be compared with one another in the comparator and undecoded addresses can be stored in the fuse bank. This provides for a low-power and space-saving design.

3. 发明申请

US20060250881A1 Memory arrangement having a plurality of RAM chips 有权
标题翻译：具有多个RAM芯片的存储装置
公开(公告)号：US20060250881A1
公开(公告)日：2006-11-09
申请号：US11394142
申请日：2006-03-30
申请人： Helmut Kandolf , Sven Kalms , Maksim Kuzmenka , Michael Hausmann
发明人： Helmut Kandolf , Sven Kalms , Maksim Kuzmenka , Michael Hausmann
IPC分类号： G11C8/00
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1027 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C8/12 , G11C11/4096
摘要： Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing and transmitting n respective parallel data bits as a packet between an n-bit parallel port and the data buses, and having a selection device which responds to selection bits in order to select a respective separate cell group within the plurality of the chips for each of the disjoint m-bit groups (d) of the n-bit packet. The k chips are classified into q=2 disjoint chip groups, each of which comprises k/q chips which differ as little as possible from one another in terms of their distance from the register. The number m is chosen to be equal to q*n/k, and the selection device is designed to select a respective separate chip from the same chip group and a cell group in this chip for each m-bit group of the same n-bit packet.
摘要翻译：本发明的实施例提供了具有物理间隔RAM芯片的偶数k = 4的存储器布置，其中每一个都可以经由m位数据总线同时写入或读取m个数据项，该m位数据总线也具有寄存器用于将n个相应的并行数据位作为n位并行端口和数据总线之间的分组进行缓冲存储和发送，并且具有响应于选择位的选择装置，以便选择多个 n位数据包的每个不相交的m位组（d）的芯片。 k个芯片被分类为q = 2个不相交的芯片组，每个芯片组包括在距离寄存器的距离方面彼此相差尽可能小的k / q个芯片组。数字m被选择为等于q * n / k，并且选择装置被设计为从相同芯片组中的每个m位组的该芯片中选择相应的单独芯片和单元组，位数据包。

4. 发明授权

US06816406B2 Magnetic memory configuration 有权
标题翻译：磁记忆体配置
公开(公告)号：US06816406B2
公开(公告)日：2004-11-09
申请号：US10715023
申请日：2003-11-17
申请人： Heinz Hönigschmid , Helmut Kandolf , Stefan Lammers
发明人： Heinz Hönigschmid , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C1114
CPC分类号： G11C11/16
摘要： A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.

5. 发明授权

US06515890B2 Integrated semiconductor memory having memory cells with a ferroelectric memory property 有权
标题翻译：具有具有铁电存储器特性的存储单元的集成半导体存储器
公开(公告)号：US06515890B2
公开(公告)日：2003-02-04
申请号：US09780305
申请日：2001-02-09
申请人： Robert Esterl , Helmut Kandolf , Heinz Hönigschmid , Thomas Röhr
发明人： Robert Esterl , Helmut Kandolf , Heinz Hönigschmid , Thomas Röhr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.
摘要翻译：集成半导体存储器具有具有铁电存储器特性的存储单元。存储器单元在每种情况下都连接在列线和充电线之间。列线连接到提供输出信号的读取放大器。充电线连接到向给定电位提供充电线的驱动器电路。在非活动模式下，列线和充电线在读取放大器或驱动电路中共同连接到用于共同供电电位的连接。结果，线之间的电位的相对快速的均衡是可能的。因此，避免了由于干扰电压引起的存储器单元内容的意外变化。

6. 发明授权

US07362650B2 Memory arrangement having a plurality of RAM chips 有权
标题翻译：具有多个RAM芯片的存储装置
公开(公告)号：US07362650B2
公开(公告)日：2008-04-22
申请号：US11394142
申请日：2006-03-30
申请人： Helmut Kandolf , Sven Kalms , Maksim Kuzmenka , Michael Hausmann
发明人： Helmut Kandolf , Sven Kalms , Maksim Kuzmenka , Michael Hausmann
IPC分类号： G11C8/00
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1027 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C8/12 , G11C11/4096
摘要： Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing and transmitting n respective parallel data bits as a packet between an n-bit parallel port and the data buses, and having a selection device which responds to selection bits in order to select a respective separate cell group within the plurality of the chips for each of the disjoint m-bit groups (d) of the n-bit packet. The k chips are classified into q=2 disjoint chip groups, each of which comprises k/q chips which differ as little as possible from one another in terms of their distance from the register. The number m is chosen to be equal to q*n/k, and the selection device is designed to select a respective separate chip from the same chip group and a cell group in this chip for each m-bit group of the same n-bit packet.
摘要翻译：本发明的实施例提供了具有物理间隔RAM芯片的偶数k = 4的存储器布置，其中每一个都可以经由m位数据总线同时写入或读取m个数据项，该m位数据总线也具有寄存器用于将n个相应的并行数据位作为n位并行端口和数据总线之间的分组进行缓冲存储和发送，并且具有响应于选择位的选择装置，以便选择多个 n位数据包的每个不相交的m位组（d）的芯片。 k个芯片被分类为q = 2个不相交的芯片组，每个芯片组包括在距离寄存器的距离方面彼此相差尽可能小的k / q个芯片组。数字m被选择为等于q * n / k，并且选择装置被设计为从相同芯片组中的每个m位组的该芯片中选择相应的单独芯片和单元组，位数据包。

7. 发明授权

US06657916B2 Integrated memory with memory cell array 有权
标题翻译：集成存储器与存储单元阵列
公开(公告)号：US06657916B2
公开(公告)日：2003-12-02
申请号：US10054195
申请日：2002-01-22
申请人： Heinz Hönigschmid , Stefan Lammers , Helmut Kandolf
发明人： Heinz Hönigschmid , Stefan Lammers , Helmut Kandolf
IPC分类号： G11C800
CPC分类号： G11C8/00 , G11C8/08
摘要： An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.
摘要翻译：集成存储器具有存储单元阵列，其存储单元连接到字线和位线。为了从一个存储单元读取或写入存储单元，第一字线可以通过可控的第一开关器件连接到电源电路，并且第二字线可以经由可控的第二开关器件连接到电源电路。根据第一字线的激活状态，控制电路可以根据第二字线和第二开关器件的激活状态来驱动第一开关器件。因此，当前未使用的现有字线可用于寻址存储单元之一。结果，字线只需要一个接线面。

8. 发明授权

US06639829B2 Configuration and method for the low-loss writing of an MRAM 有权
公开(公告)号：US06639829B2
公开(公告)日：2003-10-28
申请号：US09922471
申请日：2001-08-03
申请人： Dietmar Gogl , Helmut Kandolf , Stefan Lammers
发明人： Dietmar Gogl , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C1100
CPC分类号： G11C5/063 , G11C11/15 , G11C11/16
摘要： A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2

9. 发明申请

US20050027923A1 Hub chip for one or more memory modules 有权
标题翻译： Hub芯片用于一个或多个内存模块
公开(公告)号：US20050027923A1
公开(公告)日：2005-02-03
申请号：US10877139
申请日：2004-06-25
申请人： Sven Kalms , Helmut Kandolf
发明人： Sven Kalms , Helmut Kandolf
IPC分类号： G06F13/00 , G06F13/16
CPC分类号： G06F13/16
摘要： One embodiment of the invention provides a hub chip comprising: an address bus input for receiving a plurality of successively sent portions of address and/or command data, a shift register which has register elements and is connected to the address bus input to receive the plurality of portions of the address and/or command data, the shift register being connected to the address bus input so that, when the address and/or command data are received, the portions of the address and/or command data are successively written to the register elements, an address bus output for outputting the received address and/or command data, a memory module interface for connecting one or more memory modules, where the hub chip addresses none, one or a plurality of the connected memory modules, depending on the address and/or command data transferred, and a driver element provided to output the received portion of the address and/or command data to the address bus output before all of the portions of the address and/or command data have been received in full.
摘要翻译：本发明的一个实施例提供了一种集线器芯片，其包括：地址总线输入，用于接收地址和/或命令数据的多个连续发送的部分;移位寄存器，具有寄存器元件，并连接到地址总线输入端以接收多个地址和/或命令数据的一部分，移位寄存器连接到地址总线输入，使得当地址和/或命令数据被接收时，地址和/或命令数据的部分被连续写入到寄存器元件，用于输出接收到的地址和/或命令数据的地址总线输出，用于连接一个或多个存储器模块的存储器模块接口，其中集线器芯片不依赖于所连接的存储器模块，一个或多个连接的存储器模块，地址和/或命令数据，以及提供的驱动器元件，用于在地址总线输出的所有部分之前将地址和/或命令数据的接收部分输出到地址总线输出已收到地址和/或命令数据。

10. 发明授权

US06473335B2 MRAM configuration 有权
标题翻译： MRAM配置
公开(公告)号：US06473335B2
公开(公告)日：2002-10-29
申请号：US09898222
申请日：2001-07-03
申请人： Thomas Böhm , Helmut Kandolf , Stefan Lammers
发明人： Thomas Böhm , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.
摘要翻译：描述了一种磁阻随机存取存储器（MRAM）配置，其中线路驱动器电路分别经由连接节点分配给两个存储单元阵列，结果是驱动器电路的面积实际上可以减半。因此，获得节省空间的架构和更有效的MRAM配置。

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