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    • 2. 发明授权
    • Phase detector and phase-locked loop
    • 相位检测器和锁相环
    • US09444471B2
    • 2016-09-13
    • US14895267
    • 2013-06-06
    • Gennady Mihaylovich Vydolob
    • Gennady Mihaylovich Vydolob
    • H03L7/089H03D13/00H03L7/091H03L7/107
    • H03L7/0891H03D13/004H03L7/089H03L7/091H03L7/1077
    • A phase detector for generating a phase difference signal indicative of a phase difference between a first bi-level signal of frequency F1 and a second bi-level signal of frequency F2 is proposed. The phase detector may include first and second detector inputs, first and second flip-flops, a NAND gate, and a first and second overphase detection units. An output of the first overphase detection unit may be connected to a direct input of the second flip-flop and may be arranged to output the level “1” in response to F1≦F2 and the level “0” in response to F1>F2. An output of the second overphase detection unit may be connected to a direct input of the first flip-flop and may be arranged to output the level “1” in response to F2≦F1 and the level “0” in response to F2>F1.
    • 提出了一种相位检测器,用于产生指示频率F1的第一双电平信号和频率为F2的第二双电平信号之间的相位差的相位差信号。 相位检测器可以包括第一和第二检测器输入,第一和第二触发器,NAND门以及第一和第二超相位检测单元。 第一上相检测单元的输出可以连接到第二触发器的直接输入,并且可以被布置为响应于F1≤F2而输出电平“1”,并响应于F1> F2输出电平“0” 。 第二过相检测单元的输出可以连接到第一触发器的直接输入,并且可以被布置为响应于F2≤F1而输出电平“1”,并且响应于F2> F1而输出电平“0” 。