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1. 发明授权

US09379717B2 Apparatus to reduce power of a charge pump 有权
标题翻译：降低电荷泵功率的装置
公开(公告)号：US09379717B2
公开(公告)日：2016-06-28
申请号：US14129505
申请日：2013-11-08
申请人： Gennady Goltman , Yongping Fan , Kuan-Yueh Shen
发明人： Gennady Goltman , Yongping Fan , Kuan-Yueh Shen
IPC分类号： H03L7/00 , H03L7/08 , H03L7/085 , H03L7/089
CPC分类号： H03L7/0802 , H03L7/085 , H03L7/089 , H03L7/0895 , H03L7/093
摘要： Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.
摘要翻译：描述了一种降低电荷泵功率的装置。所述装置包括：第一延迟单元，用于接收参考时钟，所述第一延迟单元向第一顺序单元提供延迟的参考时钟; 第二延迟单元，用于接收反馈时钟，所述第二延迟单元向第二顺序单元提供延迟的反馈时钟; 用于接收参考和反馈时钟的第一逻辑单元，所述逻辑单元对所接收的参考和反馈时钟执行逻辑或运算，并且产生用于第三顺序单元的触发信号; 以及第二逻辑单元，用于接收第一和第二顺序单元的输出，并且产生耦合到第三顺序单元的输出。

2. 发明申请

US20140266308A1 CLOCK AMPLITUDE DETECTION 有权
标题翻译：时钟振幅检测
公开(公告)号：US20140266308A1
公开(公告)日：2014-09-18
申请号：US13836951
申请日：2013-03-15
申请人： Gennady Goltman , Yongping Fan
发明人： Gennady Goltman , Yongping Fan
IPC分类号： H03L7/085 , G01R23/02
CPC分类号： H03L5/00 , G01R19/04 , G01R19/16576 , H03L7/099
摘要： In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level.
摘要翻译：在一些实施例中，公开了一种AC振幅检测器，用于将AC信号的幅度与检测器阈值电平进行比较，并提供关于AC幅度是大于还是小于检测器阈值电平的指示。

3. 发明授权

US06295595B1 Method and structure for accessing a reduced address space of a defective memory 有权
标题翻译：用于访问缺陷存储器的缩减地址空间的方法和结构
公开(公告)号：US06295595B1
公开(公告)日：2001-09-25
申请号：US09295934
申请日：1999-04-21
申请人： Eli Wildenberg , Gennady Goltman
发明人： Eli Wildenberg , Gennady Goltman
IPC分类号： G06F1120
CPC分类号： G11C29/76 , G11C8/10 , G11C29/88 , G11C29/883
摘要： A circuit and method for producing defect tolerant high density memory cells at a low cost is disclosed. Rather than using redundant memory cells to salvage a memory circuit having non-functional memory cells, an address mapping circuit is used to remap addresses for non-functional memory cells into addresses for functional memory cells. Specifically, if the memory array of a memory circuit includes non-functional memory cells, an address mapping scheme is selected to reduce the effective size of the memory circuit so only functional memory cells are addressed. Because redundant memory cells are not included in the memory circuit, the semiconductor area and the cost of the memory circuit is reduced.
摘要翻译：公开了一种以低成本生产缺陷耐受性高密度存储单元的电路和方法。地址映射电路不是使用冗余存储器单元来挽救具有非功能存储器单元的存储器电路，而是用于将非功能存储器单元的地址重新映射到功能存储器单元的地址中。具体来说，如果存储器电路的存储器阵列包括非功能存储单元，则选择地址映射方案以减小存储器电路的有效大小，从而仅寻址功能存储单元。由于冗余存储单元不包括在存储器电路中，所以存储电路的半导体区域和成本降低。

4. 发明授权

US06421276B1 Method and apparatus for controlling erase operations of a non-volatile memory system 有权
标题翻译：用于控制非易失性存储器系统的擦除操作的方法和装置
公开(公告)号：US06421276B1
公开(公告)日：2002-07-16
申请号：US09927277
申请日：2001-08-09
申请人： Gennady Goltman
发明人： Gennady Goltman
IPC分类号： G11C1606
CPC分类号： G11C16/0475 , G11C16/16
摘要： A non-volatile memory system having an array of 2-bit cells is provided, wherein each cell stores an odd bit and an even bit. An ERASE pulse is applied to either the odd bits or the even bits in response to an ODD_EVEN control signal, which toggles in response to an ERASE pulse. A first ERASE pulse is applied to the odd bits. An erase verify operation is then performed until failing. The erase verify operation will likely fail on an even bit, which has not yet received an ERASE pulse. After the erase verify operation fails, a second ERASE pulse is applied to the even bits in response to the toggled ODD_EVEN control signal. The erase verify operation then resumes until this operation fails, or is successfully completed. This process continues until the erase verify operation is successful. A similar method enables a plurality of NVM blocks to be erased.
摘要翻译：提供具有2位单元阵列的非易失性存储器系统，其中每个单元存储奇数位和偶位。响应于ODD_EVEN控制信号，将ERASE脉冲施加到奇数位或偶数位，该ODD_EVEN控制信号响应于ERASE脉冲而切换。第一个ERASE脉冲被施加到奇数位。然后执行擦除验证操作直到发生故障。擦除验证操作可能会在尚未接收到擦除脉冲的偶数位上失败。在擦除验证操作失败之后，响应于切换的ODD_EVEN控制信号，向偶数位施加第二擦除脉冲。擦除验证操作然后恢复，直到此操作失败或成功完成。这个过程一直持续到擦除验证操作成功。类似的方法使得可以擦除多个NVM块。

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