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1. 发明授权

US08378728B1 Level shifting flip-flop 有权
标题翻译：电平转换触发器
公开(公告)号：US08378728B1
公开(公告)日：2013-02-19
申请号：US13487243
申请日：2012-06-03
申请人： Gaurav Goyal , Abhishek Mahajan , Bipin B. Malhan
发明人： Gaurav Goyal , Abhishek Mahajan , Bipin B. Malhan
IPC分类号： H03K3/356 , H03L5/00
CPC分类号： H03K3/35625
摘要： A level shifting flip-flop for generating a level-shifted output signal based on an input signal includes a master stage and a slave stage. The slave stage has an integrated level shifting circuit. The slave stage level shifts a signal as it passes through the flip-flop, which eliminates the need of level shifting the signal after it is output from the flip-flop.
摘要翻译：用于基于输入信号产生电平移位的输出信号的电平移动触发器包括主级和从级。从站具有集成电平移位电路。从机级电平在信号通过触发器时移位信号，这消除了在从触发器输出信号之后对信号进行电平移位的需要。

2. 发明授权

US08432189B1 Digital voltage level shifter 有权
标题翻译：数字电压电平转换器
公开(公告)号：US08432189B1
公开(公告)日：2013-04-30
申请号：US13356615
申请日：2012-01-23
申请人： Bipin B. Malhan , Gaurav Goyal , Umesh Chandra Lohani
发明人： Bipin B. Malhan , Gaurav Goyal , Umesh Chandra Lohani
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： A dual supply bidirectional level shifter performs voltage level shifting in two directions, low to high and high to low. A feedback control branch and a control stage inverter are provided that reduce leakage power and allow for low delay time while also allowing for a small circuit footprint.
摘要翻译：双电源双向电平转换器在两个方向上执行电压电平转换，从低到高，从高到低。提供反馈控制分支和控制级反相器，其减少泄漏功率并允许低延迟时间，同时还允许小的电路占用面积。

3. 发明授权

US08723582B1 Level shifter circuit 有权
标题翻译：电平移位电路
公开(公告)号：US08723582B1
公开(公告)日：2014-05-13
申请号：US13771025
申请日：2013-02-19
申请人： Gaurav Goyal , Gaurav Gupta , Bipin B. Malhan
发明人： Gaurav Goyal , Gaurav Gupta , Bipin B. Malhan
IPC分类号： H03L5/00
CPC分类号： H03K19/00 , H03K19/00361 , H03K19/018507
摘要： A single supply level shifter circuit for shifting the voltage level of an input voltage includes a voltage translation stage and a driver stage. The voltage translation stage receives the input voltage and a voltage supply and generates a first voltage. When a magnitude of the input voltage is LOW, the first voltage is LOW. The first voltage is provided to the driver stage, which inverts the first voltage to generate an output voltage that is at a voltage supply (Vdd) level, thereby level shifting the input voltage.
摘要翻译：用于移动输入电压的电压电平的单个电源电平移位器电路包括电压转换级和驱动级。电压转换级接收输入电压和电压源并产生第一电压。当输入电压的大小为低电平时，第一电压为低电平。将第一电压提供给驱动级，其使第一电压反相以产生处于电压供应（Vdd）电平的输出电压，从而对输入电压进行电平移位。

4. 发明授权

US08350592B1 Single supply digital voltage level shifter 有权
标题翻译：单电源数字电压电平转换器
公开(公告)号：US08350592B1
公开(公告)日：2013-01-08
申请号：US13356626
申请日：2012-01-23
申请人： Bipin B. Malhan , Gaurav Goyal , Umesh Chandra Lohani
发明人： Bipin B. Malhan , Gaurav Goyal , Umesh Chandra Lohani
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： A single-supply digital voltage level shifter has a first inverter having a first input for receiving an input signal with a first voltage swing, and a first output for outputting a first output signal. A second inverter has a second input for receiving the first output signal, and a second output for outputting a second output signal with a second voltage swing, where the second output signal is a level-shifted version of the input signal. A comparison stage includes a first comparison stage input for receiving the input signal, a second comparison stage input for receiving the second output signal, and a comparison stage output for outputting a comparison stage output control signal. A control stage is connected in a circuit branch of the first inverter and has a control stage switch that assumes a non-conducting state dependent on a logical state of the comparison stage output control signal.
摘要翻译：单电源数字电压电平转换器具有第一反相器，其具有用于接收具有第一电压摆幅的输入信号的第一输入端和用于输出第一输出信号的第一输出。第二反相器具有用于接收第一输出信号的第二输入端和用于输出具有第二电压摆幅的第二输出信号的第二输出端，其中第二输出信号是输入信号的电平移位版本。比较级包括用于接收输入信号的第一比较级输入端，用于接收第二输出信号的第二比较级输入端和用于输出比较级输出控制信号的比较级输出端。控制级连接在第一反相器的电路支路中，并具有控制级开关，该控制级开关取决于比较级输出控制信号的逻辑状态的非导通状态。

5. 发明授权

US09311438B1 Signal delay flip-flop cell for fixing hold time violation 有权
标题翻译：用于固定保持时间违规的信号延迟触发器单元
公开(公告)号：US09311438B1
公开(公告)日：2016-04-12
申请号：US14509037
申请日：2014-10-07
申请人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidhartha Taneja
发明人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidhartha Taneja
IPC分类号： G06F17/50 , H03K3/037 , H03K3/012
CPC分类号： G06F17/5031 , G06F2217/02 , G06F2217/84 , H03K3/012 , H03K3/0372 , H03K3/0375
摘要： A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.
摘要翻译：用于解决IC中的保持时间冲突的信号延迟单元具有第一多路复用器，其具有第一功能数据输入节点和扫描数据输入节点TI，第二多路复用器具有第二功能数据输入节点，第二输入节点连接到第一多路复用器和触发器模块的输出。施加到第一多路复用器的数据输入信号的传播被延迟，并且通过第一多路复用器的传输来增加触发器模块的保持余量。信号延迟单元可用于替换具有扫描数据保持问题的触发器，并且还用于解决相同或另一个单元中的功能数据违例。

6. 发明申请

US20160098506A1 SIGNAL DELAY FLIP-FLOP CELL FOR FIXING HOLD TIME VIOLATION 有权
标题翻译：信号延迟翻转细胞固定持续时间
公开(公告)号：US20160098506A1
公开(公告)日：2016-04-07
申请号：US14509037
申请日：2014-10-07
申请人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidharrtha Taneja
发明人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidharrtha Taneja
IPC分类号： G06F17/50 , H03K3/012 , H03K3/037
CPC分类号： G06F17/5031 , G06F2217/02 , G06F2217/84 , H03K3/012 , H03K3/0372 , H03K3/0375
摘要： A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.
摘要翻译：用于解决IC中的保持时间冲突的信号延迟单元具有第一多路复用器，其具有第一功能数据输入节点和扫描数据输入节点TI，第二多路复用器具有第二功能数据输入节点，第二输入节点连接到第一多路复用器和触发器模块的输出。施加到第一多路复用器的数据输入信号的传播被延迟，并且通过第一多路复用器的传输来增加触发器模块的保持余量。信号延迟单元可用于替换具有扫描数据保持问题的触发器，并且还用于解决相同或另一个单元中的功能数据违例。

7. 发明申请

US20150333556A1 SINGLE POWER SUPPLY LEVEL SHIFTER 有权
标题翻译：单电源电平变压器
公开(公告)号：US20150333556A1
公开(公告)日：2015-11-19
申请号：US14280655
申请日：2014-05-18
申请人： Gaurav Goyal
发明人： Gaurav Goyal
IPC分类号： H02J7/02 , H02J7/04 , H02J7/00
CPC分类号： H02J7/022 , H02J7/0042 , H02J7/045 , H02J7/345 , H02J2001/008 , H03K19/01707 , H03K19/018521
摘要： A single power supply level shifter has first and second inverters in tandem that invert an input signal from a first voltage domain and provide a first inverted signal and an output signal in a second voltage domain. A charging control circuit charges a capacitor towards the second voltage when the input signal is high, and conducts a discharge current from the capacitor during a transition of the input signal from high to low to accelerate a corresponding transition of the first inverted signal from low to high. A third inverter controls a current reduction transistor in series with the first inverter, and a third control transistor connected between the input and the charging control circuit to accelerate the flow of discharge current during the transition of the input signal from high to low.
摘要翻译：单个电源电平移位器具有串联的第一和第二反相器，它们反转来自第一电压域的输入信号，并在第二电压域中提供第一反相信号和输出信号。当输入信号为高电平时，充电控制电路使电容器朝向第二电压充电，并且在输入信号从高电平变化到低电平期间，从电容器传导放电电流，以加速第一反相信号从低电平转移到高。第三反相器控制与第一反相器串联的电流减小晶体管，以及连接在输入和充电控制电路之间的第三控制晶体管，以在输入信号从高变为低期间加速放电电流的流动。

8. 发明授权

US09154135B1 Spare gate cell for integrated circuit 有权
标题翻译：用于集成电路的备用栅极单元
公开(公告)号：US09154135B1
公开(公告)日：2015-10-06
申请号：US14262795
申请日：2014-04-27
申请人： Reecha Jajodia , Gaurav Goyal
发明人： Reecha Jajodia , Gaurav Goyal
IPC分类号： H01L25/00 , H03K19/00 , H03K19/177 , H03K19/173 , H03K19/003
CPC分类号： H03K19/17724 , H03K19/00392 , H03K19/1736 , H03K19/17748 , H03K19/17764
摘要： Spare gate cells for inclusion in an integrated circuit have multiple inputs and outputs and are capable of selectively performing, concurrently, multiple logic functions on signals appearing at the inputs. Selection of required logic functions depends on the connections of at least one of the inputs of the spare cell. One of the outputs is fed back to an input of the spare gate cell to provide certain functionality while other outputs are set to a fixed logical value. The spare gate cell may be configured to perform NOR, OR and inverter operations on inputs simultaneously.
摘要翻译：用于包含在集成电路中的备用门单元具有多个输入和输出，并且能够对出现在输入端的信号选择性地执行多个逻辑功能。所需逻辑功能的选择取决于备用单元的至少一个输入的连接。其中一个输出被反馈到备用门单元的输入以提供某些功能，而其他输出被设置为固定的逻辑值。备用门单元可以被配置为同时对输入执行NOR，OR或逆变器操作。

9. 发明授权

US08867694B1 Modular gray code counter 有权
标题翻译：模块化灰色代码计数器
公开(公告)号：US08867694B1
公开(公告)日：2014-10-21
申请号：US13945937
申请日：2013-07-19
申请人： Naman Gupta , Gaurav Goyal , Rohit Goyal
发明人： Naman Gupta , Gaurav Goyal , Rohit Goyal
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/005
摘要： A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.
摘要翻译：格雷码计数器具有多个两位格雷码计数器模块，时钟门控集成单元（CGIC）和奇偶校验位发生器。提供给两位计数器模块的CGIC门控时钟信号降低了动态功耗。奇偶校验位产生器产生一个奇偶校验位，它表示计数状态下的二进制计数。

10. 发明授权

US09306576B2 Modular gray code counter 有权
标题翻译：模块化灰色代码计数器
公开(公告)号：US09306576B2
公开(公告)日：2016-04-05
申请号：US14495876
申请日：2014-09-24
申请人： Naman Gupta , Gaurav Goyal , Rohit Goyal
发明人： Naman Gupta , Gaurav Goyal , Rohit Goyal
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/005
摘要： A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.
摘要翻译：格雷码计数器具有多个两位格雷码计数器模块，时钟门控集成单元（CGIC）和奇偶校验位发生器。提供给两位计数器模块的CGIC门控时钟信号降低了动态功耗。奇偶校验位产生器产生一个奇偶校验位，它表示计数状态下的二进制计数。

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