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1. 发明授权

US06931561B2 Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain using a plurality of storage and multiplexer components 失效
标题翻译：使用多个存储和多路复用器组件异步地连接高速时钟域和低速时钟域的装置和方法
公开(公告)号：US06931561B2
公开(公告)日：2005-08-16
申请号：US09978357
申请日：2001-10-16
申请人： Gary Dale Carpenter , Tung Nguyen Pham
发明人： Gary Dale Carpenter , Tung Nguyen Pham
IPC分类号： G06F5/06 , H04L7/02 , G06F1/12 , H04L7/00
CPC分类号： G06F5/06 , H04L7/02
摘要： Interfacing circuitry for asynchronously transferring data between a high-speed clock domain and a low-speed clock domain is provided. The interfacing circuitry is divided into halves, with one half being synchronized to a first clock and the second half being synchronized to a second clock. The first half and the second half are mirror images of each other. Each half has at least one storage component, such as a register and a flip-flop, for storing a valid bit as well as data, and at least one multiplexer component for gating the storage component. The valid bit is used to control the multiplexer at a receiving half. When transferring from a high-speed clock domain to a low-speed clock domain, the high-speed clock domain may probe the received data and/or the valid bit stored in the low-speed clock domain before the high-speed clock domain sends additional data.
摘要翻译：提供了在高速时钟域和低速时钟域之间异步传输数据的接口电路。接口电路被分成两半，其中一半与第一时钟同步，而后半部分与第二时钟同步。上半场和下半场是彼此的镜像。每一半具有用于存储有效位和数据的至少一个存储组件，例如寄存器和触发器，以及用于门控存储组件的至少一个多路复用器组件。有效位用于在接收端控制多路复用器。当从高速时钟域传输到低速时钟域时，高速时钟域可以在高速时钟域发送之前探测存储在低速时钟域中的接收数据和/或有效位附加数据。

2. 发明授权

US09251913B2 Infrastructure for performance based chip-to-chip stacking 有权
标题翻译：基于性能的芯片到芯片堆叠的基础设施
公开(公告)号：US09251913B2
公开(公告)日：2016-02-02
申请号：US13156836
申请日：2011-06-09
申请人： Gary Dale Carpenter , Alan James Drake , Eren Kursun , Phillip John Restle
发明人： Gary Dale Carpenter , Alan James Drake , Eren Kursun , Phillip John Restle
IPC分类号： G01R27/28 , G11C29/02 , G01R31/28 , G11C7/10 , H01L25/065 , G11C29/50
CPC分类号： G11C29/025 , G01R31/2882 , G11C7/10 , G11C29/50012 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.
摘要翻译：在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的基础设施的方法和系统。关键路径监控电路（基础设施）被配置为从第一层中的发射点发射信号，第一层是第一电路。基础设施还被配置为创建到捕获点的电路径。信号从第一层的发射点发射。测量电路径的性能特征，从而进行测量，其中测量表示当与3D堆叠中的第二层堆叠时的第一层的性能，而不会在3D堆叠中实际堆叠第一层和第二层，第二层是第二电路。

3. 发明授权

US07669013B2 Directory for multi-node coherent bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US07669013B2
公开(公告)日：2010-02-23
申请号：US11828439
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。如果在本地节点的多节点桥接处接收到的请求是系统请求，则执行本地节点目录的查找。如果目录项指示请求中指定的数据具有本地所有者或本地目标，则请求将转发到本地节点。如果本地节点确定请求是本地请求，则执行本地节点目录的查找。如果目录条目指示请求中指定的数据具有本地所有者和本地目标，则解析本地节点上的数据的一致性，并且如果需要，则执行请求数据的传输。否则，请求将转发到多节点系统中的所有远程节点。

4. 发明申请

US20090031086A1 Directory For Multi-Node Coherent Bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US20090031086A1
公开(公告)日：2009-01-29
申请号：US11828448
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/16
CPC分类号： G06F12/0822
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。本地节点确定请求是本地还是系统请求。如果请求是本地请求，则执行本地节点中的目录的查找。如果本地节点目录中的条目指示请求中的数据不具有远程所有者，并且请求没有远程目标，则在本地节点上解析数据的一致性，并且传输如果需要，请求中指定的数据将被执行，并且请求是本地请求。如果条目指示数据具有远程所有者或请求具有远程目标，则将请求转发到多节点系统中的所有远程节点。

5. 发明申请

US20090031085A1 Directory for Multi-Node Coherent Bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US20090031085A1
公开(公告)日：2009-01-29
申请号：US11828439
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/16
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。如果在本地节点的多节点桥接处接收到的请求是系统请求，则执行本地节点目录的查找。如果目录项指示请求中指定的数据具有本地所有者或本地目标，则请求将转发到本地节点。如果本地节点确定请求是本地请求，则执行本地节点目录的查找。如果目录条目指示请求中指定的数据具有本地所有者和本地目标，则解析本地节点上的数据的一致性，并且如果需要，则执行请求数据的传输。否则，请求将转发到多节点系统中的所有远程节点。

6. 发明授权

US06269428B1 Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system 失效
标题翻译：用于避免由于在非均匀存储器访问系统内的无效事务的碰撞而产生活动锁的方法和系统
公开(公告)号：US06269428B1
公开(公告)日：2001-07-31
申请号：US09259367
申请日：1999-02-26
申请人： Gary Dale Carpenter , Mark Edward Dean , David Brian Glasco
发明人： Gary Dale Carpenter , Mark Edward Dean , David Brian Glasco
IPC分类号： G06F1200
CPC分类号： G06F12/0828 , G06F12/0813
摘要： A method for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system is disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to a request by a processor of a first node to invalidate a remote copy of a cache line also stored within its cache memory at substantially the same time when a processor of a second node is also requesting to invalidate said cache line, one of the two requests is allowed to complete. The allowed request is the first request to complete without retry at the point of coherency, typically the home node. Subsequently, the other one of the two requests is permitted to complete.
摘要翻译：公开了一种用于避免由于在非均匀存储器访问系统内的无效事务的冲突而导致的活动锁定的方法。 NUMA计算机系统包括耦合到互连的至少两个节点。两个节点中的每一个包括本地系统存储器。响应于第一节点的处理器在第二节点的处理器也要求使所述高速缓存行无效的基本上同时存储在其高速缓冲存储器中的高速缓存行的远端副本的请求时，这两个请求被允许完成。允许的请求是第一个完成的请求，而不是在一致性的时候重试，通常是家庭节点。随后，两个请求中的另一个被允许完成。

7. 发明授权

US6145032A System for recirculation of communication transactions in data processing in the event of communication stall 失效
标题翻译：在通信失速的情况下数据处理中通信事务的再循环系统
公开(公告)号：US6145032A
公开(公告)日：2000-11-07
申请号：US157894
申请日：1998-09-21
申请人： John Peyton Bannister , Gary Dale Carpenter , David Brian Glasco
发明人： John Peyton Bannister , Gary Dale Carpenter , David Brian Glasco
IPC分类号： H04L12/56 , G06F3/00
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9031
摘要： A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.
摘要翻译：用于数据处理系统的数据再循环装置包括至少一个输出缓冲器，数据从该输出缓冲器输出到互连上，多个输入存储区域，数据被选择用于存储在输出缓冲器内;以及选择逻辑，其从多个输入存储区域用于存储在输出缓冲器内。此外，数据再循环装置包括缓冲器控制逻辑，其响应于确定特定数据在输出缓冲器中停滞而导致特定数据从输出缓冲器中移除并存储在多个输入存储器地区在一个实施例中，再循环数据具有专用输入存储区域。

8. 发明授权

US07443195B2 Method of transparently reducing power consumption of a high-speed communication link 失效
标题翻译：透明地降低高速通信链路的功耗的方法
公开(公告)号：US07443195B2
公开(公告)日：2008-10-28
申请号：US10773427
申请日：2004-02-09
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H03K19/0175 , G05F1/10
CPC分类号： H03K19/0008
摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.
摘要翻译：提供一种在保持性能特性的同时降低功耗并避免嵌入在SOC中的高速通信链路的昂贵的过度设计的方法。该方法包括以降低的电压合成通信链路，以确定和隔离与非电源电压关键的电路相关的电源电压关键的电路。电源电压关键电路包含不降低电压而不降低通信链路性能特性的组件。使用非降低电压来驱动电源电压关键电路，同时使用降低的电压来驱动非电源电压关键电路。使用嵌入在通信链路中的电压调节器来产生降低的电压。

9. 发明授权

US06275907B1 Reservation management in a non-uniform memory access (NUMA) data processing system 失效
标题翻译：非均匀内存访问（NUMA）数据处理系统中的预留管理
公开(公告)号：US06275907B1
公开(公告)日：2001-08-14
申请号：US09184395
申请日：1998-11-02
申请人： Yoanna Baumgartner , Gary Dale Carpenter , Mark Edward Dean , Anna Elman , James Stephen Fields, Jr. , David Brian Glasco
发明人： Yoanna Baumgartner , Gary Dale Carpenter , Mark Edward Dean , Anna Elman , James Stephen Fields, Jr. , David Brian Glasco
IPC分类号： G06F1208
CPC分类号： G06F12/0828 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node. If the processor within the remote processing node has a reservation for a memory granule among the plurality of memory granules that is not resident within the associated cache hierarchy, the coherence directory associates the memory granule with a coherence state indicating that the reserved memory granule may possibly be held non-exclusively at the remote processing node. In this manner, the coherence mechanism can be utilized to manage processor reservations even in cases in which a reserving processor's cache hierarchy does not hold a copy of the reserved memory granule.
摘要翻译：非均匀存储器访问（NUMA）计算机系统包括耦合到节点互连的多个处理节点。多个处理节点至少包括一个远程处理节点，其包含具有相关联的高速缓存层级的处理器和家庭处理节点。家庭处理节点包括包含多个存储器颗粒的共享系统存储器和指示存储在除家庭处理节点之外的至少一个处理节点中的多个存储器颗粒中的存储器颗粒的副本的可能的相干状态的一致性目录。如果远程处理节点内的处理器对于不驻留在相关联的高速缓存层级中的多个存储器颗粒中的存储器颗粒进行预留，则相干目录将存储器颗粒与指示保留的存储器颗粒可能的相干状态相关联不排他地保存在远程处理节点。以这种方式，即使在保留处理器的高速缓存层级不保留预留的存储器颗粒的副本的情况下，也可以利用相干机制来管理处理器预留。

10. 发明授权

US6081874A Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect 失效
标题翻译：推测在节点互连上发出请求的非均匀内存访问（NUMA）数据处理系统
公开(公告)号：US6081874A
公开(公告)日：2000-06-27
申请号：US162828
申请日：1998-09-29
申请人： Gary Dale Carpenter , Mark Edward Dean , David Brian Glasco , Richard Nicholas Iachetta, Jr.
发明人： Gary Dale Carpenter , Mark Edward Dean , David Brian Glasco , Richard Nicholas Iachetta, Jr.
IPC分类号： G06F15/163 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0813
摘要： A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.
摘要翻译：非均匀存储器访问（NUMA）数据处理系统包括至少第一处理节点和第二处理节点耦合到的节点互连。第一处理节点和第二处理节点各自包括本地互连，耦合到本地互连的处理器，耦合到本地互连的系统存储器，以及插入在本地互连和节点互连之间的节点控制器。为了减少通信延迟，第一处理节点的节点控制器通过节点互连将从第一处理节点的本地互连接收的请求事务推测发送到第二处理节点。在一个实施例中，第一处理节点的节点控制器随后将状态信号发送到第二处理节点的节点控制器，以便指示如何在第二处理节点处理请求事务。

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