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1. 发明授权

US07622942B2 Method and apparatus for measuring device mismatches 失效
标题翻译：用于测量设备不匹配的方法和设备
公开(公告)号：US07622942B2
公开(公告)日：2009-11-24
申请号：US12147024
申请日：2008-06-26
申请人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
发明人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G11C11/41 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004 , G11C2029/5006
摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
摘要翻译：用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

2. 发明申请

US20080258752A1 METHOD AND APPARATUS FOR MEASURING DEVICE MISMATCHES 失效
标题翻译：用于测量设备错配的方法和装置
公开(公告)号：US20080258752A1
公开(公告)日：2008-10-23
申请号：US12147024
申请日：2008-06-26
申请人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
发明人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G11C11/41 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004 , G11C2029/5006
摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
摘要翻译：用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

3. 发明授权

US07408372B2 Method and apparatus for measuring device mismatches 有权
标题翻译：用于测量设备不匹配的方法和设备
公开(公告)号：US07408372B2
公开(公告)日：2008-08-05
申请号：US11422913
申请日：2006-06-08
申请人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
发明人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G11C11/41 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004 , G11C2029/5006
摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
摘要翻译：用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

4. 发明申请

US20070296442A1 Method and Apparatus for Measuring Device Mismatches 有权
标题翻译：用于测量设备不匹配的方法和设备
公开(公告)号：US20070296442A1
公开(公告)日：2007-12-27
申请号：US11422913
申请日：2006-06-08
申请人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
发明人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G11C11/41 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004 , G11C2029/5006
摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
摘要翻译：用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

5. 发明授权

US07885798B2 Closed-loop modeling of gate leakage for fast simulators 有权
标题翻译：用于快速模拟器的栅极泄漏的闭环建模
公开(公告)号：US07885798B2
公开(公告)日：2011-02-08
申请号：US11746976
申请日：2007-05-10
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
IPC分类号： G06F17/50 , G06F7/62
CPC分类号： G06F17/5036
摘要： A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.
摘要翻译：一种使用网表的电路仿真方法，其中具有未建模的非线性行为的第一器件通过插入具有接近未建模的非线性行为的非线性响应的第二器件而被修改。第一器件可以是例如第一晶体管，并且第二器件可以是可变电流源，特别是其中电流在表示第一晶体管（栅极至源极或栅极 -排水）。在仿真电路期间，控制诸如第二晶体管的栅极至源极电压的参数来模拟栅极泄漏。模型参数可以是第一晶体管技术的栅极的有效量子机械氧化物厚度值的函数。

6. 发明申请

US20080281570A1 Closed-Loop Modeling of Gate Leakage for Fast Simulators 有权
标题翻译：闸模泄漏闭环建模快速模拟器
公开(公告)号：US20080281570A1
公开(公告)日：2008-11-13
申请号：US11746976
申请日：2007-05-10
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.
摘要翻译：一种使用网表的电路仿真方法，其中具有未建模的非线性行为的第一器件通过插入具有接近未建模的非线性行为的非线性响应的第二器件而被修改。第一器件可以是例如第一晶体管，并且第二器件可以是可变电流源，特别是其中电流在表示第一晶体管（栅极至源极或栅极 -排水）。在仿真电路期间，控制诸如第二晶体管的栅极至源极电压的参数来模拟栅极泄漏。模型参数可以是第一晶体管技术的栅极的有效量子机械氧化物厚度值的函数。

7. 发明申请

US20080278182A1 Test Structure for Statistical Characterization of Metal and Contact/Via Resistances 审中-公开
标题翻译：金属和接触/通孔电阻的统计表征的测试结构
公开(公告)号：US20080278182A1
公开(公告)日：2008-11-13
申请号：US11746766
申请日：2007-05-10
申请人： Kanak B. Agarwal , Ying Liu , Sani R. Nassif
发明人： Kanak B. Agarwal , Ying Liu , Sani R. Nassif
IPC分类号： G01R27/08
CPC分类号： G01R31/2884 , G01R31/31855 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A test structure for measuring resistances of a large number of interconnect elements such as metal, contacts and vias includes an array of test cells in rows and columns. Power is selectively supplied to test cells in a given column while current is selectively steered from test cells in a given row. A first voltage near the power input node of a device under test (DUT) is selectively sensed, and a second voltage near the current measurement tap is selectively sensed. The resistance of the DUT is the difference of the first and second voltages divided by the current. Additional voltage taps are provided for test cells having multiple resistive elements. This array of test cells can be used to characterize the statistical distribution of resistance variation and to identify physical location of defects in resistive elements.
摘要翻译：用于测量诸如金属，触点和通孔的大量互连元件的电阻的测试结构包括行和列中的测试单元的阵列。选择性地将功率供给到给定列中的测试单元，同时从给定行中的测试单元选择性地导向电流。有选择地感测被测设备（DUT）的功率输入节点附近的第一电压，并选择性地感测当前测量分接头附近的第二电压。 DUT的电阻是第一和第二电压除以电流的差值。为具有多个电阻元件的测试单元提供额外的电压抽头。这种测试单元阵列可用于表征电阻变化的统计分布，并确定电阻元件中缺陷的物理位置。

8. 发明申请

US20070164769A1 Active cancellation matrix for process parameter measurements 失效
标题翻译：用于过程参数测量的主动消除矩阵
公开(公告)号：US20070164769A1
公开(公告)日：2007-07-19
申请号：US11333612
申请日：2006-01-17
申请人： Fadi Gebara , Ying Liu , Jayakumaran Sivagnaname , Ivan Vo
发明人： Fadi Gebara , Ying Liu , Jayakumaran Sivagnaname , Ivan Vo
IPC分类号： G01R31/26
CPC分类号： G11C29/50 , G01R31/3004 , G11C2029/5002 , G11C2029/5006
摘要： An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.
摘要翻译：用于过程参数测量的主动消除矩阵为每个测试位置提供反馈路径，其中每个反馈路径用于感测所施加的电压，并且所感测的电压用于调整沿着输入路径的任何变化的源电压。被测设备被布置成行和列阵列，并且反馈和电压输入路径沿着相应的轨道形成，该轨道大致平行于被测试的器件的一排。选择器用于选择性地将测试节点的输出路由到诸如电流传感器的测量单元。可以改变输入电压以在各种条件下为器件建立电流 - 电压（I-V）曲线。在被测器件为晶体管的示例中，每个源极输入包括用于漏极电压，源极电压和栅极电压的三个电压输入（导线）。

9. 发明申请

US20080284461A1 ACTIVE CANCELLATION MATRIX FOR PROCESS PARAMETER MEASUREMENTS 审中-公开
标题翻译：用于过程参数测量的主动消除矩阵
公开(公告)号：US20080284461A1
公开(公告)日：2008-11-20
申请号：US12141899
申请日：2008-06-18
申请人： Fadi H. Gebara , Ying Liu , Jayakumaran Sivagnaname , Ivan Vo
发明人： Fadi H. Gebara , Ying Liu , Jayakumaran Sivagnaname , Ivan Vo
IPC分类号： G01R31/26
CPC分类号： G11C29/50 , G01R31/3004 , G11C2029/5002 , G11C2029/5006
摘要： An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.
摘要翻译：用于过程参数测量的主动消除矩阵为每个测试位置提供反馈路径，其中每个反馈路径用于感测所施加的电压，并且所感测的电压用于调整沿着输入路径的任何变化的源电压。被测设备被布置成行和列阵列，并且反馈和电压输入路径沿着相应的轨道形成，该轨道大体上平行于一行被测器件延伸。选择器用于选择性地将测试节点的输出路由到诸如电流传感器的测量单元。可以改变输入电压以在各种条件下为器件建立电流 - 电压（I-V）曲线。在被测器件为晶体管的示例中，每个源极输入包括用于漏极电压，源极电压和栅极电压的三个电压输入（导线）。

10. 发明授权

US07394276B2 Active cancellation matrix for process parameter measurements 失效
标题翻译：用于过程参数测量的主动消除矩阵
公开(公告)号：US07394276B2
公开(公告)日：2008-07-01
申请号：US11333612
申请日：2006-01-17
申请人： Fadi H. Gebara , Ying Liu , Jayakumaran Sivagnaname , Ivan Vo
发明人： Fadi H. Gebara , Ying Liu , Jayakumaran Sivagnaname , Ivan Vo
IPC分类号： G01R31/26
CPC分类号： G11C29/50 , G01R31/3004 , G11C2029/5002 , G11C2029/5006
摘要： An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.
摘要翻译：用于过程参数测量的主动消除矩阵为每个测试位置提供反馈路径，其中每个反馈路径用于感测所施加的电压，并且所感测的电压用于调整沿着输入路径的任何变化的源电压。被测设备被布置成行和列阵列，并且反馈和电压输入路径沿着相应的轨道形成，该轨道大体上平行于一行被测器件延伸。选择器用于选择性地将测试节点的输出路由到诸如电流传感器的测量单元。可以改变输入电压以在各种条件下为器件建立电流 - 电压（I-V）曲线。在被测器件为晶体管的示例中，每个源极输入包括用于漏极电压，源极电压和栅极电压的三个电压输入（导线）。

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