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1. 发明授权

US5360758A Self-aligned buried strap for trench type DRAM cells 失效
标题翻译：用于沟槽型DRAM单元的自对准埋地带
公开(公告)号：US5360758A
公开(公告)日：1994-11-01
申请号：US161823
申请日：1993-12-03
申请人： Gary B. Bronner , John K. DeBrosse , Donald M. Kenney
发明人： Gary B. Bronner , John K. DeBrosse , Donald M. Kenney
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10829
摘要： A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.
摘要翻译：具有浅沟槽隔离的深沟槽型DRAM单元具有掩埋多晶硅带，其被限定为不使用单独的掩模，通过在浅沟槽清晰度之前在至少深沟槽上沉积带材料并且使用浅沟槽隔离掩模部分地重叠深沟槽，从而在切割浅沟槽的过程中限定带子。

2. 发明授权

US5684313A Vertical precharge structure for DRAM 失效
标题翻译： DRAM的垂直预充电结构
公开(公告)号：US5684313A
公开(公告)日：1997-11-04
申请号：US603832
申请日：1996-02-20
申请人： Donald M. Kenney
发明人： Donald M. Kenney
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108
摘要： A DRAM one device cell and an associated precharge circuit are integrated together in a novel structure having an area of only four square features. The structure also provides physical and electrical separation between adjacent cells along a direction parallel to the DRAM word lines. The DRAM bit line length per bit is reduced by 50% relative to a conventional planar integrated structure disclosed elsewhere. As a result, bit line capacitance is also substantially reduced, and the effectiveness of a precharge technique for reduction of DRAM power consumption is enhanced by the dense novel structure.
摘要翻译： DRAM一个器件单元和相关联的预充电电路以仅具有四个正方形特征的区域的新颖结构集成在一起。该结构还沿着与DRAM字线平行的方向在相邻单元之间提供物理和电气分离。相对于其他地方公开的常规平面集成结构，每位的DRAM位线长度减小了50％。结果，位线电容也显着降低，并且通过密集的新颖结构增强了用于减少DRAM功耗的预充电技术的有效性。

3. 发明授权

US4801988A Semiconductor trench capacitor cell with merged isolation and node trench construction 失效
标题翻译：具有并联隔离和节点沟槽结构的半导体沟槽电容器单元
公开(公告)号：US4801988A
公开(公告)日：1989-01-31
申请号：US925570
申请日：1986-10-31
申请人： Donald M. Kenney
发明人： Donald M. Kenney
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L29/78
CPC分类号： H01L29/66181 , H01L27/10829 , H01L29/945
摘要： A semiconductor trench capacitor construction having a self-aligned isolation structure formed within the trench. The trench isolation structure consists of a thick isolating layer formed along the upper portion of the trench side walls. The trench isolation structure facilitates larger capacitor constructions and allows the capacitors to abut adjacent capacitors and other devices.
摘要翻译：一种半导体沟槽电容器结构，其具有形成在沟槽内的自对准隔离结构。沟槽隔离结构由沿着沟槽侧壁的上部形成的厚的隔离层组成。沟槽隔离结构有助于更大的电容器结构，并允许电容器邻接相邻的电容器和其他器件。

4. 发明授权

US4326332A Method of making a high density V-MOS memory array 失效
标题翻译：制造高密度V-MOS存储器阵列的方法
公开(公告)号：US4326332A
公开(公告)日：1982-04-27
申请号：US173508
申请日：1980-07-28
申请人： Donald M. Kenney
发明人： Donald M. Kenney
IPC分类号： H01L27/10 , H01L21/306 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L29/74 , H01L29/749 , H01L29/78 , H01L21/265 , H01L21/308
CPC分类号： H01L27/10876 , H01L21/30608 , H01L21/76877 , H01L27/10823 , Y10S438/901
摘要： A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer having a plurality of parallel thick and thin regions. Holes are etched in portions of the thin regions with the use of an etch mask defining a plurality of parallel regions aligned perpendicular to the regions in the masking layer. V-MOSFET devices having self-aligned gate electrodes are formed in the holes and device interconnecting lines are formed under the remaining portions of the thin regions. A combination of anisotropic etching and directionally dependent etching, such as reaction ion etching, may be used to extend the depth of V-grooves. A method of eliminating the overhang of a masking layer after anisotropic etching includes the oxidation of the V-groove followed by etching to remove both the grown oxide and the overhang is also disclosed.
摘要翻译：一种用于提供高密度动态存储单元的方法，其通过使用具有多个平行的厚和薄区域的器件限定掩模层来提供两个V-MOSFET器件元件及其互连的自对准。使用限定垂直于掩模层中的区域排列的多个平行区域的蚀刻掩模，在薄区域的部分中蚀刻孔。在孔中形成具有自对准栅电极的V-MOSFET器件，并且在薄区的其余部分之下形成器件互连线。可以使用各向异性蚀刻和方向依赖蚀刻的组合，例如反应离子蚀刻来延长V形槽的深度。还公开了在各向异性蚀刻之后消除掩模层的突出部的方法，包括V型槽的氧化，然后进行蚀刻以去除生长的氧化物和悬垂两者。

5. 发明授权

US5719080A Semiconductor trench capacitor cell having a buried strap 失效
公开(公告)号：US5719080A
公开(公告)日：1998-02-17
申请号：US522204
申请日：1995-08-31
申请人： Donald M. Kenney
发明人： Donald M. Kenney
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861
摘要： A semiconductor trench capacitor structure having a first level aligned isolation structure and buried strap that extends from within the trench into the doped semiconductor substrate. The semiconductor trench capacitor structure may be fabricated by forming a shallow trench within the trench capacitor and semiconductor substrate, depositing a layer of conductive material within the shallow trench, using a mask to define and recess the strap and depositing insulating material within the shallow trench.

6. 发明授权

US5710057A SOI fabrication method 失效
标题翻译： SOI制造方法
公开(公告)号：US5710057A
公开(公告)日：1998-01-20
申请号：US679021
申请日：1996-07-12
申请人： Donald M. Kenney
发明人： Donald M. Kenney
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76251 , H01L21/7806 , H01L2221/68363 , Y10S117/915 , Y10S148/012
摘要： A first region of a seed substrate is separated from a bonded handle substrate by etching and/or fracturing a second region of the seed substrate. A third region of the seed substrate remains bonded to the handle wafer. Etching and etch ant distribution are facilitated by capillary action in trenches formed in the seed substrate prior to bonding of the handle substrate. A portion of the second region may be removed by undercut etching prior to handle bonding. Elevated pressure and etchant composition are used to suppress bubble formation during etching. Alternatively, pressure from bubble formation is used to fracture a portion of the second region. First, second, and third regions are defined by a variety of methods.
摘要翻译：通过蚀刻和/或压裂种子基底的第二区域将种子基底的第一区域与结合的手柄基底分离。种子基底的第三区域保持结合到处理晶片。通过在接合手柄衬底之前在种子衬底中形成的沟槽中的毛细管作用促进蚀刻和蚀刻蚂蚁分布。在处理粘合之前，可以通过底切蚀刻去除第二区域的一部分。压力升高和蚀刻剂组成用于抑制蚀刻期间的气泡形成。或者，使用来自气泡形成的压力来破坏第二区域的一部分。第一，第二和第三区域由各种方法定义。

7. 发明授权

US5521118A Sidewall strap 失效
标题翻译：侧壁带
公开(公告)号：US5521118A
公开(公告)日：1996-05-28
申请号：US440574
申请日：1995-05-15
申请人： Chung H. Lam , James S. Nakos , Donald M. Kenney , Eric Adler
发明人： Chung H. Lam , James S. Nakos , Donald M. Kenney , Eric Adler
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/485 , H01L21/283
CPC分类号： H01L27/10861 , H01L21/76897 , H01L23/485 , H01L2924/0002 , Y10S257/90
摘要： The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising an outer surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.
摘要翻译：本发明是提供连接至少两个导电区域的导电路径的侧壁连接器。侧壁连接器具有包括外表面的顶部部分。导电构件接触顶部，将轨道连接到导电区域或外部导体。位于导电区域上的蚀刻停止层可用于在定向蚀刻期间保护导电区域以形成侧壁连接器。然后使用导电桥连接导电区域和导电侧壁导轨的暴露部分，导电桥延伸跨越蚀刻停止层的厚度。通过该过程形成“T”连接器，从一对相交的侧壁开始，其中两个侧壁具有与其相交的不同高度的顶部边缘。连接器用于形成用于DRAM单元的带子。

8. 发明授权

US5412246A Low temperature plasma oxidation process 失效
标题翻译：低温等离子体氧化工艺
公开(公告)号：US5412246A
公开(公告)日：1995-05-02
申请号：US186568
申请日：1994-01-26
申请人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
发明人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
IPC分类号： C23C8/36 , H01L21/31 , H01L21/316 , H01L21/321 , H01L21/8242 , H01L27/108 , H01L29/12
CPC分类号： H01L21/32105 , H01L21/02238 , H01L21/02252 , H01L21/31662 , Y10S148/118 , Y10S257/90
摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (
摘要翻译：一种在半导体器件的表面上形成薄膜的工艺。该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1，在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。

9. 发明授权

US5399516A Method of making shadow RAM cell having a shallow trench EEPROM 失效
标题翻译：制造具有浅沟槽EEPROM的阴影RAM单元的方法
公开(公告)号：US5399516A
公开(公告)日：1995-03-21
申请号：US930797
申请日：1992-09-21
申请人： Albert S. Bergendahl , Claude L. Bertin , John E. Cronin , Howard L. Kalter , Donald M. Kenney , Chung H. Lam , Hsing-San Lee
发明人： Albert S. Bergendahl , Claude L. Bertin , John E. Cronin , Howard L. Kalter , Donald M. Kenney , Chung H. Lam , Hsing-San Lee
IPC分类号： H01L27/10 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/308
CPC分类号： H01L29/7882 , H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/115
摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.
摘要翻译：公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。本发明的阵列提供高密度影子RAM。还公开了用于制造本发明的装置的方法。

10. 发明授权

US5365097A Vertical epitaxial SOI transistor, memory cell and fabrication methods 失效
标题翻译：垂直外延SOI晶体管，存储单元和制造方法
公开(公告)号：US5365097A
公开(公告)日：1994-11-15
申请号：US958195
申请日：1992-10-05
申请人： Donald M. Kenney
发明人： Donald M. Kenney
IPC分类号： H01L27/108 , H01L29/786 , H01L29/68 , H01L29/06
CPC分类号： H01L27/10841 , H01L29/78642
摘要： Vertical epitaxial SOI transistors and memory cells are disclosed. The devices are formed completely within a substrate trench and have a bulk channel epitaxially grown on an exposed surface of the substrate within the trench. The bulk channel is disposed proximate to a transistor gate electrode such that an inversion layer is formed therein when the gate electrode is appropriately biased. Back biasing of the bulk region is accomplished through the substrate. In the transistor embodiment, a first node diffusion and a second node diffusion are disposed at opposite ends of the bulk channel. In a memory cell configuration the access transistor is disposed above a trench storage node, which electrically connects with the transistor's second node diffusion. Arrays of the trench transistors and trench memory cells are also described. Further, fabrication methods for the various structures disclosed are presented. A novel wiring approach to construction of bit lines in a cell array is also set forth.
摘要翻译：公开了垂直外延SOI晶体管和存储单元。器件完全在衬底沟槽内形成，并具有外延生长在沟槽内的衬底的暴露表面上的体沟道。本体通道靠近晶体管栅极设置，使得当栅电极被适当偏置时，形成反转层。本体区域的反向偏压是通过衬底实现的。在晶体管实施例中，第一节点扩散和第二节点扩散设置在大容量沟道的相对端。在存储单元配置中，存取晶体管设置在与晶体管的第二节点扩散电连接的沟槽存储节点的上方。还描述了沟槽晶体管和沟槽存储器单元的阵列。此外，提出了所公开的各种结构的制造方法。还阐述了在单元阵列中构造位线的新颖的布线方法。

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