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1. 发明授权

US5625779A Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge 失效
标题翻译：仲裁信令机制，以防止死锁保证访问延迟，并保证扩展桥的采集延迟
公开(公告)号：US5625779A
公开(公告)日：1997-04-29
申请号：US366964
申请日：1994-12-30
申请人： Gary A. Solomon , Peter D. MacWilliams , George R. Hayek , Nicholas D. Wade , Abid Asghar
发明人： Gary A. Solomon , Peter D. MacWilliams , George R. Hayek , Nicholas D. Wade , Abid Asghar
IPC分类号： G06F13/364 , G06F13/40 , G06F13/36
CPC分类号： G06F13/364 , G06F13/4031 , G06F13/4036
摘要： An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.
摘要翻译：耦合在扩展桥和主桥之间的中间总线的仲裁信令机制，用于管理通过中间总线的通信。主桥包括用于在CPU和扩展桥之间发布事务的CPU发布缓冲器，以及用于存储要写入到DRAM中的数据的DRAM缓冲器。主桥还包括耦合以从扩展桥接器和耦合到扩展桥的任何其它总线代理接收请求信号的仲裁器。响应于扩展桥的请求，仲裁器在确认确认信号之前清空CPU发布缓冲区和DRAM缓冲区。提供了一种被动释放方法，其包括在扩展桥具有总线控制的通信周期期间通过扩展桥信令发送被动释放语义。主桥可以在再次允许进入扩建桥之前，暂时使用公交车给另一个总线代理。

2. 发明授权

US6112016A Method and apparatus for sharing a signal line between agents 失效
标题翻译：用于在代理之间共享信号线的方法和装置
公开(公告)号：US6112016A
公开(公告)日：2000-08-29
申请号：US824632
申请日：1997-03-27
申请人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
发明人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
摘要翻译：介绍了高速外设总线的内存总线扩展。具体来说，边带信号用于将高速缓存属性映射，高速缓存一致性周期和双处理器支持的高级机制覆盖到高速外设总线上。在高速缓存属性映射的情况下，先前处理器和高速缓存中支持的三个高速缓存存储器属性信号被保持三个原始信号的所有功能的两个高速缓存属性信号所取代。在缓存一致性周期的情况下，提供高级操作模式。这些包括支持快速写入，通过缓存对完全高速缓存行写入的写回数据的丢弃以及允许高速缓存提供响应于存储器读取的数据的读取干预。在双处理器支持的情况下，呈现了用于支持双处理器的几个新信号和相关协议。具体支持分为以下三个方面：扩展侦听以支持多个缓存，支持两个处理器之间的共享数据，以及提供处理器和升级仲裁协议，允许双处理器共享一个授权信号线。

3. 发明授权

US5822767A Method and apparartus for sharing a signal line between agents 失效
标题翻译：用于在代理之间共享信号线的方法和应用程序
公开(公告)号：US5822767A
公开(公告)日：1998-10-13
申请号：US824927
申请日：1997-03-27
申请人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
发明人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
摘要翻译：介绍了高速外设总线的内存总线扩展。具体来说，边带信号用于将高速缓存属性映射，高速缓存一致性周期和双处理器支持的高级机制覆盖到高速外设总线上。在高速缓存属性映射的情况下，先前处理器和高速缓存中支持的三个高速缓存存储器属性信号被保持三个原始信号的所有功能的两个高速缓存属性信号所取代。在缓存一致性周期的情况下，提供高级操作模式。这些包括支持快速写入，通过缓存对完全高速缓存行写入的写回数据的丢弃以及允许高速缓存提供响应于存储器读取的数据的读取干预。在双处理器支持的情况下，呈现了用于支持双处理器的几个新信号和相关协议。具体支持分为以下三个方面：扩展侦听以支持多个缓存，支持两个处理器之间的共享数据，以及提供处理器和升级仲裁协议，允许双处理器共享一个授权信号线。

4. 发明授权

US5651137A Scalable cache attributes for an input/output bus 失效
标题翻译：输入/输出总线的可扩展缓存属性
公开(公告)号：US5651137A
公开(公告)日：1997-07-22
申请号：US420494
申请日：1995-04-12
申请人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
发明人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
摘要翻译：介绍了高速外设总线的内存总线扩展。具体来说，边带信号用于将高速缓存属性映射，高速缓存一致性周期和双处理器支持的高级机制覆盖到高速外设总线上。在高速缓存属性映射的情况下，先前处理器和高速缓存中支持的三个高速缓存存储器属性信号被保持三个原始信号的所有功能的两个高速缓存属性信号所取代。在缓存一致性周期的情况下，提供高级操作模式。这些包括支持快速写入，通过缓存对完全高速缓存行写入的写回数据的丢弃以及允许高速缓存提供响应于存储器读取的数据的读取干预。在双处理器支持的情况下，呈现了用于支持双处理器的几个新信号和相关协议。具体支持分为以下三个方面：扩展侦听以支持多个缓存，支持两个处理器之间的共享数据，以及提供处理器和升级仲裁协议，允许双处理器共享一个授权信号线。

5. 发明授权

US5948094A Method and apparatus for executing multiple transactions within a single arbitration cycle 失效
标题翻译：在单个仲裁周期内执行多个事务的方法和装置
公开(公告)号：US5948094A
公开(公告)日：1999-09-07
申请号：US932745
申请日：1997-09-17
申请人： Gary A. Solomon , Norman J. Rasmussen , Peter D. MacWilliams
发明人： Gary A. Solomon , Norman J. Rasmussen , Peter D. MacWilliams
IPC分类号： G06F13/362 , G06F13/14
CPC分类号： G06F13/3625
摘要： A method of arbitrating among bus agents, wherein a bus agent is permitted multiple transactions within a single arbitration cycle. An arbitration event is initiated, and a request from a bus agent is granted to that bus agent for executing a transaction. A timer is started and the transaction is executed. If the timer does not expire before the transaction is completed, another request from that same bus agent is granted to the bus agent for executing an additional transaction before a subsequent arbitration event is initiated.
摘要翻译：一种在总线代理之间进行仲裁的方法，其中总线代理被允许在单个仲裁周期内的多个事务。启动仲裁事件，并向总线代理授予来自总线代理的请求以执行事务。启动定时器并执行事务。如果定时器在事务完成之前没有到期，那么来自该相同总线代理的另一个请求将被授予总线代理，以便在后续仲裁事件发起之前执行附加事务。

6. 发明授权

US06633947B1 Memory expansion channel for propagation of control and request packets 失效
标题翻译：用于传播控制和请求数据包的内存扩展通道
公开(公告)号：US06633947B1
公开(公告)日：2003-10-14
申请号：US09154063
申请日：1998-09-16
申请人： Thomas J. Holman , Peter D. MacWilliams
发明人： Thomas J. Holman , Peter D. MacWilliams
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , G06F13/4243
摘要： A memory system comprising an expansion buffer and a memory expansion channel for connecting a large array of memory devices, such as Direct RDRAMs, to a memory controller. The memory devices are partitioned into subsets of memory devices so that each subset is connected to a unique memory channel for sending and receiving data. The expansion buffer and memory expansion channel provide communication with the memory devices via control packets on the expansion bus, where each control packet has a channel identification field to store a channel identifier; and via request packets on the expansion bus, where each request packet is associated with a control packet. The expansion buffer routes a request packet to a unique channel based upon the channel identifier stored in the associated control packet.
摘要翻译：一种存储器系统，包括扩展缓冲器和用于将诸如Direct RDRAM的大量存储器件连接到存储器控制器的存储器扩展通道。存储器件被划分为存储器件的子集，使得每个子集连接到用于发送和接收数据的唯一存储器通道。扩展缓冲器和存储器扩展通道通过扩展总线上的控制分组提供与存储器件的通信，其中每个控制分组具有用于存储信道标识符的信道标识字段; 并且经由扩展总线上的请求分组，其中每个请求分组与控制分组相关联。扩展缓冲器基于存储在相关联的控制分组中的信道标识符将请求分组路由到唯一信道。

7. 发明授权

US06405271B1 Data flow control mechanism for a bus supporting two-and three-agent transactions 失效
标题翻译：支持二代理和三代理交易的总线数据流控制机制
公开(公告)号：US06405271B1
公开(公告)日：2002-06-11
申请号：US08709215
申请日：1996-09-06
申请人： Peter D. MacWilliams , Nitin V. Sarangdhar , Stephen S. Pawlowski , Gurbir Singh
发明人： Peter D. MacWilliams , Nitin V. Sarangdhar , Stephen S. Pawlowski , Gurbir Singh
IPC分类号： G06F1300
CPC分类号： G06F13/368 , G06F13/36 , G06F13/37 , G06F13/4213
摘要： A data flow control mechanism for a bus supporting two- and three-agent transactions includes a control logic to place an indication of a request onto a computer system bus. The agent placing the indication on the bus then waits to place data corresponding to the request onto the bus until it has received an indication from another agent coupled to the bus that the other agent is ready to receive the data.
摘要翻译：支持二代理和三代理交易的总线的数据流控制机制包括一个将请求的指示置于计算机系统总线上的控制逻辑。在总线上放置指示的代理然后等待将与该请求相对应的数据放置在总线上，直到其接收到来自耦合到总线的另一代理程序的指示，即其他代理程序准备好接收数据。

8. 发明授权

US06253302B1 Method and apparatus for supporting multiple overlapping address spaces on a shared bus 失效
公开(公告)号：US06253302B1
公开(公告)日：2001-06-26
申请号：US08705684
申请日：1996-08-29
申请人： Peter D. MacWilliams , Stephen S. Pawlowski
发明人： Peter D. MacWilliams , Stephen S. Pawlowski
IPC分类号： G06F1200
CPC分类号： G06F11/1016 , G06F12/0623
摘要： A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

9. 发明授权

US5513331A Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset 失效
标题翻译：用于在系统复位期间自动配置具有不确定数量的不确定尺寸的存储器单元的存储器子系统的计算机系统的系统存储器地址空间的方法和装置
公开(公告)号：US5513331A
公开(公告)日：1996-04-30
申请号：US412607
申请日：1995-03-29
申请人： Stephen Pawlowski , Peter D. MacWilliams
发明人： Stephen Pawlowski , Peter D. MacWilliams
IPC分类号： G06F12/06 , G06F12/02
CPC分类号： G06F12/0684 , G06F12/0661
摘要： An apparatus and method for assigning memory address information in a computer system. The present invention relates to computer systems having a plurality of ports or slots for coupling boards or other apparatus accessible to a processor of the computer system. The computer system further comprises an address decoder electrically coupled with the ports and processor. The address decoder receives, preferably at the time the computer system is first powered on, memory size identifying information from each of the memory boards coupled with the plurality of slots. The address decoder assigns system address space to each of the individual memories.
摘要翻译：一种用于在计算机系统中分配存储器地址信息的装置和方法。本发明涉及具有多个端口或槽的计算机系统，用于连接板或可由计算机系统的处理器访问的其它设备。计算机系统还包括与端口和处理器电耦合的地址解码器。地址解码器优选地在计算机系统首次通电时接收来自与多个时隙耦合的每个存储器板的存储器大小识别信息。地址解码器为各个存储器分配系统地址空间。

10. 发明授权

US5488639A Parallel multistage synchronization method and apparatus 失效
标题翻译：并行多级同步方法及装置
公开(公告)号：US5488639A
公开(公告)日：1996-01-30
申请号：US171554
申请日：1993-12-21
申请人： Peter D. MacWilliams , Dror Avni , Avi Liebermensch , Anan Baransy , Robert L. Farrell
发明人： Peter D. MacWilliams , Dror Avni , Avi Liebermensch , Anan Baransy , Robert L. Farrell
IPC分类号： H04L7/02 , H04L7/033 , H04L7/00
CPC分类号： H04L7/02 , H04L7/0338 , H04L7/0337
摘要： A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first enable line, to the second sampling circuit by a second enable line, and to the third sampling circuit by a third enable line. The first, second, and third sampling circuits are coupled to receive the asynchronous signal. The selecting circuit is coupled to receive the output signals of the first, second and third sampling circuits. For the first sampling circuit, the following steps are performed: sampling the asynchronous signal, generating an output signal for the sampling circuit, waiting a period of time, and selecting the sampling circuit's output signal. These steps are also performed for the second sampling circuit and the third sampling circuit.
摘要翻译：一种用于将异步信号同步到时钟信号的方法和装置。该装置包括使能发生器，第一，第二和第三采样电路，选择电路，并且可以包括锁存电路。使能发生器通过第一使能线耦合到第一采样电路，通过第二使能线耦合到第二采样电路，并通过第三使能线耦合到第三采样电路。第一，第二和第三采样电路被耦合以接收异步信号。选择电路被耦合以接收第一，第二和第三采样电路的输出信号。对于第一采样电路，执行以下步骤：对异步信号进行采样，产生采样电路的输出信号，等待一段时间，并选择采样电路的输出信号。对于第二采样电路和第三采样电路也执行这些步骤。

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