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1. 发明授权

US5651137A Scalable cache attributes for an input/output bus 失效
标题翻译：输入/输出总线的可扩展缓存属性
公开(公告)号：US5651137A
公开(公告)日：1997-07-22
申请号：US420494
申请日：1995-04-12
申请人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
发明人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
摘要翻译：介绍了高速外设总线的内存总线扩展。具体来说，边带信号用于将高速缓存属性映射，高速缓存一致性周期和双处理器支持的高级机制覆盖到高速外设总线上。在高速缓存属性映射的情况下，先前处理器和高速缓存中支持的三个高速缓存存储器属性信号被保持三个原始信号的所有功能的两个高速缓存属性信号所取代。在缓存一致性周期的情况下，提供高级操作模式。这些包括支持快速写入，通过缓存对完全高速缓存行写入的写回数据的丢弃以及允许高速缓存提供响应于存储器读取的数据的读取干预。在双处理器支持的情况下，呈现了用于支持双处理器的几个新信号和相关协议。具体支持分为以下三个方面：扩展侦听以支持多个缓存，支持两个处理器之间的共享数据，以及提供处理器和升级仲裁协议，允许双处理器共享一个授权信号线。

2. 发明授权

US6112016A Method and apparatus for sharing a signal line between agents 失效
标题翻译：用于在代理之间共享信号线的方法和装置
公开(公告)号：US6112016A
公开(公告)日：2000-08-29
申请号：US824632
申请日：1997-03-27
申请人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
发明人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
摘要翻译：介绍了高速外设总线的内存总线扩展。具体来说，边带信号用于将高速缓存属性映射，高速缓存一致性周期和双处理器支持的高级机制覆盖到高速外设总线上。在高速缓存属性映射的情况下，先前处理器和高速缓存中支持的三个高速缓存存储器属性信号被保持三个原始信号的所有功能的两个高速缓存属性信号所取代。在缓存一致性周期的情况下，提供高级操作模式。这些包括支持快速写入，通过缓存对完全高速缓存行写入的写回数据的丢弃以及允许高速缓存提供响应于存储器读取的数据的读取干预。在双处理器支持的情况下，呈现了用于支持双处理器的几个新信号和相关协议。具体支持分为以下三个方面：扩展侦听以支持多个缓存，支持两个处理器之间的共享数据，以及提供处理器和升级仲裁协议，允许双处理器共享一个授权信号线。

3. 发明授权

US5822767A Method and apparartus for sharing a signal line between agents 失效
标题翻译：用于在代理之间共享信号线的方法和应用程序
公开(公告)号：US5822767A
公开(公告)日：1998-10-13
申请号：US824927
申请日：1997-03-27
申请人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
发明人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
摘要翻译：介绍了高速外设总线的内存总线扩展。具体来说，边带信号用于将高速缓存属性映射，高速缓存一致性周期和双处理器支持的高级机制覆盖到高速外设总线上。在高速缓存属性映射的情况下，先前处理器和高速缓存中支持的三个高速缓存存储器属性信号被保持三个原始信号的所有功能的两个高速缓存属性信号所取代。在缓存一致性周期的情况下，提供高级操作模式。这些包括支持快速写入，通过缓存对完全高速缓存行写入的写回数据的丢弃以及允许高速缓存提供响应于存储器读取的数据的读取干预。在双处理器支持的情况下，呈现了用于支持双处理器的几个新信号和相关协议。具体支持分为以下三个方面：扩展侦听以支持多个缓存，支持两个处理器之间的共享数据，以及提供处理器和升级仲裁协议，允许双处理器共享一个授权信号线。

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