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    • 3. 发明申请
    • Methods of Forming Semiconductor Devices
    • 形成半导体器件的方法
    • US20080113515A1
    • 2008-05-15
    • US11874267
    • 2007-10-18
    • Hyun-Chul KimSung-Il ChoEun-Young KangYong-Hyun KwonJae-Seung Hwang
    • Hyun-Chul KimSung-Il ChoEun-Young KangYong-Hyun KwonJae-Seung Hwang
    • H01L21/302
    • H01L21/3086H01L21/3088H01L21/823437H01L27/105H01L29/66621
    • A method of forming a semiconductor device is provided. The method includes preparing a semiconductor substrate to include a cell region and a peripheral region and forming a first mask layer on the semiconductor substrate. First hard mask patterns that are configured to expose the first mask layer are formed on the first mask layer in the cell region. A second mask layer that is configured to conformably cover the first hard mask patterns is formed. A second hard mask pattern is formed between the first hard mask patterns, wherein the second hard mask pattern is configured to contact a lateral surface of the second mask layer. The second mask layer interposed between the first hard mask patterns and the second hard mask pattern is removed. A plurality of trenches are etched in the semiconductor substrate of the cell region using the first hard mask patterns and the second hard mask pattern as a mask.
    • 提供一种形成半导体器件的方法。 该方法包括制备半导体衬底以包括单元区域和外围区域,并在半导体衬底上形成第一掩模层。 配置为暴露第一掩模层的第一硬掩模图案形成在单元区域中的第一掩模层上。 形成被构造为顺应地覆盖第一硬掩模图案的第二掩模层。 在第一硬掩模图案之间形成第二硬掩模图案,其中第二硬掩模图案被配置为接触第二掩模层的侧表面。 插入在第一硬掩模图案和第二硬掩模图案之间的第二掩模层被去除。 使用第一硬掩模图案和第二硬掩模图案作为掩模,在单元区域的半导体衬底中蚀刻多个沟槽。
    • 8. 发明授权
    • Methods of manufacturing a vertical type semiconductor device
    • 制造垂直型半导体器件的方法
    • US08871591B2
    • 2014-10-28
    • US13600025
    • 2012-08-30
    • Yong-Hyun KwonDae-Hyun JangSeong-Soo LeeKyoung-Sub Shin
    • Yong-Hyun KwonDae-Hyun JangSeong-Soo LeeKyoung-Sub Shin
    • H01L21/336
    • H01L21/76805H01L21/76816H01L21/76831H01L27/11556H01L27/11575H01L27/11582
    • According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.
    • 根据本发明构思的示例性实施例,一种方法包括在基板上的单元图案之间形成单元图案和绝缘夹层。 在最上面的单元图案上形成包括初始接触孔和预接触孔的上绝缘层。 形成第一反射限制层图案和第一光致抗蚀剂层图案,用于暴露第一初步接触孔,同时覆盖初始和初步接触孔的入口部分。 在第一初步接触孔下方的层上进行第一蚀刻处理,以在比第一预接触孔的底部低的位置处露出电池图案。 重复第一反射限制层图案和第一光致抗蚀剂层图案的侧壁部分的部分去除处理以及通过预接触孔的底部的暴露层上的蚀刻工艺,以形成具有不同深度的接触孔。